采用MTJ-Last工艺制备4ns, 0.9V写入电压嵌入垂直STT-MRAM

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI:10.1109/VLSI-TSA.2014.6839663

K. Ikegami, H. Noguchi, C. Kamata, M. Amano, K. Abe, K. Kushida, E. Kitagawa, T. Ochiai, N. Shimomura, A. Kawasumi, H. Hara, J. Ito, S. Fujita

{"title":"采用MTJ-Last工艺制备4ns, 0.9V写入电压嵌入垂直STT-MRAM","authors":"K. Ikegami, H. Noguchi, C. Kamata, M. Amano, K. Abe, K. Kushida, E. Kitagawa, T. Ochiai, N. Shimomura, A. Kawasumi, H. Hara, J. Ito, S. Fujita","doi":"10.1109/VLSI-TSA.2014.6839663","DOIUrl":null,"url":null,"abstract":"We evaluated embedded perpendicular spin transfer torque magnetic random access memory (STT-MRAM) performance fabricated by magnetic tunnel junction (MTJ) -“Last process”, which is able to expand material and structural design space of CMOS and MTJ, by SPICE simulation and test chip measurement. By the post-layout simulation, we show that the delay increase by parasitics, which originates from fabricating MTJ on the upper metal layer is below 50ps and negligible for most applications. And from the test chip measurement, we demonstrated switching operation as fast as 4ns, below 1V for STT-MRAM.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A 4ns, 0.9V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process\",\"authors\":\"K. Ikegami, H. Noguchi, C. Kamata, M. Amano, K. Abe, K. Kushida, E. Kitagawa, T. Ochiai, N. Shimomura, A. Kawasumi, H. Hara, J. Ito, S. Fujita\",\"doi\":\"10.1109/VLSI-TSA.2014.6839663\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We evaluated embedded perpendicular spin transfer torque magnetic random access memory (STT-MRAM) performance fabricated by magnetic tunnel junction (MTJ) -“Last process”, which is able to expand material and structural design space of CMOS and MTJ, by SPICE simulation and test chip measurement. By the post-layout simulation, we show that the delay increase by parasitics, which originates from fabricating MTJ on the upper metal layer is below 50ps and negligible for most applications. And from the test chip measurement, we demonstrated switching operation as fast as 4ns, below 1V for STT-MRAM.\",\"PeriodicalId\":403085,\"journal\":{\"name\":\"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2014.6839663\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2014.6839663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 12

摘要

通过SPICE仿真和测试芯片测量，对磁性隧道结(MTJ) -“最后工艺”制造的嵌入式垂直自旋传递转矩磁性随机存取存储器(STT-MRAM)的性能进行了评价，该存储器能够扩展CMOS和MTJ的材料和结构设计空间。通过布局后仿真，我们发现，由于在上层金属层上制造MTJ而产生的寄生效应导致的延迟增加小于50ps，对于大多数应用来说可以忽略不计。从测试芯片测量中，我们展示了STT-MRAM的开关操作速度为4ns，低于1V。

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A 4ns, 0.9V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process

We evaluated embedded perpendicular spin transfer torque magnetic random access memory (STT-MRAM) performance fabricated by magnetic tunnel junction (MTJ) -“Last process”, which is able to expand material and structural design space of CMOS and MTJ, by SPICE simulation and test chip measurement. By the post-layout simulation, we show that the delay increase by parasitics, which originates from fabricating MTJ on the upper metal layer is below 50ps and negligible for most applications. And from the test chip measurement, we demonstrated switching operation as fast as 4ns, below 1V for STT-MRAM.

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Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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