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Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)最新文献

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Stability/performance assessment of monolithic 3D 6T/8T SRAM cells considering transistor-level interlayer coupling 考虑晶体管级层间耦合的单片3D 6T/8T SRAM单元的稳定性/性能评估
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839680
M. Fan, V. Hu, Yin-Nien Chen, P. Su, C. Chuang
{"title":"Stability/performance assessment of monolithic 3D 6T/8T SRAM cells considering transistor-level interlayer coupling","authors":"M. Fan, V. Hu, Yin-Nien Chen, P. Su, C. Chuang","doi":"10.1109/VLSI-TSA.2014.6839680","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839680","url":null,"abstract":"In this work, we investigate the impact of interlayer coupling on monolithic 3D 6T/8T SRAM cells with various layouts and tier combinations. Our results indicate that for 3D 6T SRAM cell with NFET in top layer, aligning upper-tier pull-down NFET with bottom-tier pull-up PFET enables better cell stability. For monolithic 3D 8T cell, an area-efficient 4N4P design is evaluated with optimized two-tier layout to enhance cell performance. We find that stacking NFET layer over the PFET tier results in larger design margins for SRAM cell stability and performance.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122977188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cryo implanted high performance n+/p junctions in Ge for future CMOS 在Ge中低温植入高性能n+/p结，用于未来的CMOS
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839660
P. Bhatt, P. Swarnkar, A. Misra, C. Hatem, A. Nainani, S. Lodha
{"title":"Cryo implanted high performance n+/p junctions in Ge for future CMOS","authors":"P. Bhatt, P. Swarnkar, A. Misra, C. Hatem, A. Nainani, S. Lodha","doi":"10.1109/VLSI-TSA.2014.6839660","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839660","url":null,"abstract":"This work demonstrates high performance n+/p Ge junctions using cryo (-100°C) ion implantation of phosphorus, followed by a low temperature (400°C) anneal. Improvements such as higher dopant activation (21.3% vs. 14.5%), lower junction leakage due to less end-of-range damage (3.9A/cm2 vs. 11.6A/cm2), lower junction depth (220nm vs. 270nm) and lower sheet resistance (65Ω/□ vs. 87Ω/□) are demonstrated for cryo vs. room temperature (RT) phosphorus implanted n+/p junctions. Compared to RT, 7.5X reduction in off-state leakage is demonstrated on Ge nMOSFETs fabricated using a gate last process with cryo implanted junctions. Phosphorus activation is also demonstrated on cryo implanted, 25 nm wide Ge fins indicating feasibility of this process for future Ge CMOS technology.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The observation of BTI-induced RTN traps in inversion and accumulation modes on HfO2 high-k metal gate 28nm CMOS devices 在HfO2高k金属栅28nm CMOS器件上，bti诱导的RTN阱在反转和积累模式下的观察
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839679
P. Wu, E. Hsieh, P. Y. Lu, S. Chung, K. Chang, C. H. Liu, J. Ke, C. Yang, C. Tsai
{"title":"The observation of BTI-induced RTN traps in inversion and accumulation modes on HfO2 high-k metal gate 28nm CMOS devices","authors":"P. Wu, E. Hsieh, P. Y. Lu, S. Chung, K. Chang, C. H. Liu, J. Ke, C. Yang, C. Tsai","doi":"10.1109/VLSI-TSA.2014.6839679","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839679","url":null,"abstract":"A comprehensive analysis on the BTI induced RTN traps in high-k(HK) CMOS devices have been investigated in inversion (inv.) and accumulation (acc.) modes. The combination of two modes for RTN measurement provides a wide range of energy window in high-k gate dielectric, in which a simple extraction method of RTN analysis has been adopted to analyze the gate dielectric dual-layer of advanced HK devices. The results show that inversion mode measurement can only identify the RTN traps in the channel region, which is related to the Vth degradation. While, accumulation mode may detect the traps inside the gate-drain overlap region which provides better understanding of GIDL current. This basic understanding is of critical important to the quality development of HK gate dielectrics in advanced CMOS technologies.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125294341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Realizing multimode of resistive switching in single Ag/SiO2/Pt device via tuning forming compliance current 通过调整形成顺应电流，实现单Ag/SiO2/Pt器件的多模电阻开关
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839677
Haitao Sun, Qi Liu, S. Long, H. Lv, Ming Liu
{"title":"Realizing multimode of resistive switching in single Ag/SiO2/Pt device via tuning forming compliance current","authors":"Haitao Sun, Qi Liu, S. Long, H. Lv, Ming Liu","doi":"10.1109/VLSI-TSA.2014.6839677","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839677","url":null,"abstract":"Coexistence of volatile threshold switching (TS) and nonvolatile memory switching (MS) behaviors are achieved in a single Ag/SiO2/Pt device. After positive forming with high compliance current (ICC), a conductive filament (CF) consisting of continuous Ag nanocrystals is formed in the device, and the device shows bipolar MS behavior under positive SET and negative RESET. After positive forming process with low ICC, a CF consisting of discrete Ag nanocrystals is formed. The device shows two types of resistive switching behaviors based on the subsequent operation condition. Under low ICC condition, the device shows symmetrical TS in the positive and negative voltage loops. Interesting, when removing the ICC, a unipolar MS with negative differential resistance (NDR) characteristic is observed under negative voltage loop. In addition, the unipolar MS shows good performances, including high uniformity, high reliability and multilevel storage potential.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117338219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design trends and test challenges in automotive electronics 汽车电子的设计趋势和测试挑战
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839645
Li-Chao Wang
{"title":"Design trends and test challenges in automotive electronics","authors":"Li-Chao Wang","doi":"10.1109/VLSI-TSA.2014.6839645","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839645","url":null,"abstract":"Summary form only given. Electronics design has been driven by three major trends in recent years: going green, health & safety and connected intelligence. These three trends converge for automotive electronics design, driving the need for energy-efficient, intelligent and reliable chip products. This increases design complexity and demands for higher-quality products. Historically, test of automotive chip products has been a critical part to ensure that the quality demand is met. The recent trends present greater ever challenges for test of automotive chip products, including managing the enormous test data, dealing with new defect mechanisms, controlling the test cost while achieving the customer demand of zero defect rate. This talk discusses these challenges and two potential directions to overcome the challenges: Built-In Self Test (BIST) and data mining driven intelligent test. We will explain why BIST and test data mining are crucial for automotive electronics and how test is value-added for automotive chip products and not cost.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116231455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of technological and geometrical parameters on low-frequency noise in SOI omega-gate nanowire NMOSFETs 工艺和几何参数对SOI ω栅极纳米线nmosfet低频噪声的影响
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839653
M. Koyama, M. Cassé, R. Coquand, S. Barraud, G. Ghibaudo, H. Iwai, G. Reimbold
{"title":"Influence of technological and geometrical parameters on low-frequency noise in SOI omega-gate nanowire NMOSFETs","authors":"M. Koyama, M. Cassé, R. Coquand, S. Barraud, G. Ghibaudo, H. Iwai, G. Reimbold","doi":"10.1109/VLSI-TSA.2014.6839653","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839653","url":null,"abstract":"A study of the interface quality in ultra-scaled omega-gate nanowire NMOSFETs, with variant technological boosters, is presented by low-frequency noise (LFN) measurements. Excellent quality of the interfaces has been achieved down to narrow width (10nm), and whatever the technological splits. In particular, efficient tensile stressor has been demonstrated with high performance enhancement and preserved noise performance fulfilling the ITRS 1/f LFN road map.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130214253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Vertical resistive switching memory (VRRAM): A real 3D device demonstration and analysis of high-density application 垂直电阻开关存储器(VRRAM):一种真实三维器件的高密度应用演示与分析
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839683
T. Y. Wu, Y. S. Chen, P. Gu, W. Chen, H. Y. Lee, P. S. Chen, K. Tsai, C. Tsai, S. Z. Rahaman, Y. D. Lin, F. Chen, M. Tsai, T. Ku
{"title":"Vertical resistive switching memory (VRRAM): A real 3D device demonstration and analysis of high-density application","authors":"T. Y. Wu, Y. S. Chen, P. Gu, W. Chen, H. Y. Lee, P. S. Chen, K. Tsai, C. Tsai, S. Z. Rahaman, Y. D. Lin, F. Chen, M. Tsai, T. Ku","doi":"10.1109/VLSI-TSA.2014.6839683","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839683","url":null,"abstract":"The design, cost, and the operation methodology in the 2-terminal and 3-terminal VRRAM devices are studied. The real 3D vertical-contact RRAM devices are also demonstrated and the devices showed good memory performance. A self-rectifying device is proposed to suppress the sneak current in the VRRAM.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123367313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Strain response of monolayer MoS2 in the ballistic regime 弹道状态下单层MoS2的应变响应
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839672
Hung-Chih Chang, P. Chen, Fu-Liang Yang, C. W. Liu
{"title":"Strain response of monolayer MoS2 in the ballistic regime","authors":"Hung-Chih Chang, P. Chen, Fu-Liang Yang, C. W. Liu","doi":"10.1109/VLSI-TSA.2014.6839672","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839672","url":null,"abstract":"Two-dimensional (2-D) materials are perfect channels for ultra thin body (UTB) device due to the perfect electrostatic control. Graphene is the most well-known 2-D material with high mobility but lack of bandgap. To overcome the shortage of graphene-based transistors, 2-D monolayer transition metal dichalcogenides (TMD) with intrinsic bandgap (1eV~2eV) have drawn much attention. MoS2 is expected to be one of the promising candidates among all TMD materials for the channels of UTB FETs [1][2]. Strain technology is in fact responsible for an alteration of the band structure in silicon to enhance the device performance [3]. With the appropriate strain engineering on the 2-D materials, the implementation to novel technology process of high performance transistor could be realized.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126629164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of redox reactions in resistive switching processes of AlOx/WOy based bilayer RRAM AlOx/WOy双层RRAM电阻开关过程中氧化还原反应的研究
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839690
Minghao Wu, Huaqiang Wu, Xinyi Li, Ning Deng, H. Qian
{"title":"Study of redox reactions in resistive switching processes of AlOx/WOy based bilayer RRAM","authors":"Minghao Wu, Huaqiang Wu, Xinyi Li, Ning Deng, H. Qian","doi":"10.1109/VLSI-TSA.2014.6839690","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839690","url":null,"abstract":"Pulsed programming measurements were carried out to study the abrupt differences between the SET/RESET processes of the AlOx/WOy bilayer RRAM devices. Electrical measurement results showed that both SET and RESET switching are affected by the applied pulse amplitude. But the RESET operation has a strong relation with the pulse width. Calculation results indicate the RESET step needs more energy than the SET step. A combination of electrical field and joule heating is needed to complete the RESET step. A redox reaction model is proposed to explain the asymmetry characteristic of the SET/RESET operations.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114974231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Studies on read-stability and write-ability of fast access STT-MRAMs 快速存取stt - mram读写稳定性研究
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839665
T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
{"title":"Studies on read-stability and write-ability of fast access STT-MRAMs","authors":"T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh","doi":"10.1109/VLSI-TSA.2014.6839665","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839665","url":null,"abstract":"It is shown that the 4T2MTJ and the 6T2MTJ-1 STT-MRAMs are more stable than SRAM at read operation in 90 nm, partly because the imbalanced resistances RAP and RP in a pair of MTJs increase the read-stability. However, the 6T2MTJ-2 STT-MRAM is not practical because of its destructive readout feature. For the worst cell (-5σ) in the tail distribution, the read-stability margin of the 4T2MTJ STT-MRAM is larger than the 6T2MTJ-1 one.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132973697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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