考虑晶体管级层间耦合的单片3D 6T/8T SRAM单元的稳定性/性能评估

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI:10.1109/VLSI-TSA.2014.6839680

M. Fan, V. Hu, Yin-Nien Chen, P. Su, C. Chuang

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引用次数: 0

摘要

在这项工作中，我们研究了层间耦合对具有不同布局和层组合的单片3D 6T/8T SRAM单元的影响。我们的研究结果表明，对于顶层具有nfiet的3D 6T SRAM电池，将上层下拉nfiet与底层上拉pfiet对齐可以提高电池的稳定性。对于单片3D 8T电池，通过优化两层布局来评估面积高效的4N4P设计，以提高电池性能。我们发现，在fet层上堆叠fet层可以为SRAM单元的稳定性和性能带来更大的设计余量。

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Stability/performance assessment of monolithic 3D 6T/8T SRAM cells considering transistor-level interlayer coupling

In this work, we investigate the impact of interlayer coupling on monolithic 3D 6T/8T SRAM cells with various layouts and tier combinations. Our results indicate that for 3D 6T SRAM cell with NFET in top layer, aligning upper-tier pull-down NFET with bottom-tier pull-up PFET enables better cell stability. For monolithic 3D 8T cell, an area-efficient 4N4P design is evaluated with optimized two-tier layout to enhance cell performance. We find that stacking NFET layer over the PFET tier results in larger design margins for SRAM cell stability and performance.

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Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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