Cryo implanted high performance n+/p junctions in Ge for future CMOS

Abstract

This work demonstrates high performance n+/p Ge junctions using cryo (-100°C) ion implantation of phosphorus, followed by a low temperature (400°C) anneal. Improvements such as higher dopant activation (21.3% vs. 14.5%), lower junction leakage due to less end-of-range damage (3.9A/cm2 vs. 11.6A/cm2), lower junction depth (220nm vs. 270nm) and lower sheet resistance (65Ω/□ vs. 87Ω/□) are demonstrated for cryo vs. room temperature (RT) phosphorus implanted n+/p junctions. Compared to RT, 7.5X reduction in off-state leakage is demonstrated on Ge nMOSFETs fabricated using a gate last process with cryo implanted junctions. Phosphorus activation is also demonstrated on cryo implanted, 25 nm wide Ge fins indicating feasibility of this process for future Ge CMOS technology.