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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs最新文献

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An 800V integrated DMOS-IGBT/PiN or MPS-rectifier power device 800V集成DMOS-IGBT/PiN或mps -整流电源器件
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239975
R. Natarajan, K. Varadarajan, C. Hitchcock, T. Chow
{"title":"An 800V integrated DMOS-IGBT/PiN or MPS-rectifier power device","authors":"R. Natarajan, K. Varadarajan, C. Hitchcock, T. Chow","doi":"10.1109/WCT.2004.239975","DOIUrl":"https://doi.org/10.1109/WCT.2004.239975","url":null,"abstract":"A novel power device that integrates a non-punchthrough DMOS insulated gate bipolar transistor with a fast-switching, anti-parallel PiN or merged pin Schottky (MPS) rectifier is proposed and experimentally demonstrated. Integration of the anti-parallel rectifier within the power switch reduces cost, component-count and packaging parasitic of the power module. Device integration is achieved through side-by-side placement of the IGBT and PiN/MPS rectifier in the same die with both devices sharing common terminals. Experimental characteristics of the fabricated designs indicate successful device integration with competitive IGBT and diode performance in the integrated device, as compared to discrete devices. Improved reverse recovery performance of the antiparallel rectifier is evident from 30% reduction in reverse peak current and 45% reduction in reverse recovery charge due to the MPS structure as compared to a PiN.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114290174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dielectric breakdown mechanism in thick SiO/sub 2/ films revisited 重论SiO/ sub2 /厚膜的介电击穿机理
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239938
K. Kubota, Y. Kamakura, K. Taniguchi, Y. Sugahara, R. Shimizu
{"title":"Dielectric breakdown mechanism in thick SiO/sub 2/ films revisited","authors":"K. Kubota, Y. Kamakura, K. Taniguchi, Y. Sugahara, R. Shimizu","doi":"10.1109/WCT.2004.239938","DOIUrl":"https://doi.org/10.1109/WCT.2004.239938","url":null,"abstract":"The dielectric breakdown in thick (T/sub ox/>15 nm) SiO/sub 2/ films is examined, focusing on its statistical properties. Time-dependent dielectric breakdown is measured using the Fowler-Nordheim and the substrate hot hole injection techniques, under various bias conditions. It is demonstrated that in thick oxide films, the Weibull slope is a function of the stress condition, and it is much smaller than the value predicted by the percolation theory. We discuss the effect of trapped holes on the breakdown statistics.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116680728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Drain voltage dependence of on resistance in 700V super junction LDMOS transistor 700V超级结LDMOS晶体管漏极电压对电阻的依赖性
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239906
M. Quddus, L. Tu, T. Ishiguro
{"title":"Drain voltage dependence of on resistance in 700V super junction LDMOS transistor","authors":"M. Quddus, L. Tu, T. Ishiguro","doi":"10.1109/WCT.2004.239906","DOIUrl":"https://doi.org/10.1109/WCT.2004.239906","url":null,"abstract":"In this paper, the dependence of the specific on resistance R/sub DS/*A on drain voltage V/sub D/ is presented for the first time for 700 V super junction (SJ) based multi-RESURF LDMOS transistors and such results are compared to those of single-RESURF (SR) and double-RESURF (DR) LDMOS transistors. Based on ISE based 3D device simulation results, it has been demonstrated that even the decrease in the width of the NP stripes of the SJ structure results in significant improvement in R/sub DS/*A. Such improvement suffers greatly at high drain bias V/sub D/ due to an increased influence in the constriction of the current conduction path due to the large depletion effect.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133636662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
12.7kV ultra high voltage SiC commutated gate turn-off thyristor: SICGT 12.7kV超高压SiC整流栅关断晶闸管:SICGT
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240155
Y. Sugawara, D. Takayama, K. Asano, A. Agarwal, S. Ryu, J. Palmour, S. Ogata
{"title":"12.7kV ultra high voltage SiC commutated gate turn-off thyristor: SICGT","authors":"Y. Sugawara, D. Takayama, K. Asano, A. Agarwal, S. Ryu, J. Palmour, S. Ogata","doi":"10.1109/WCT.2004.240155","DOIUrl":"https://doi.org/10.1109/WCT.2004.240155","url":null,"abstract":"A novel 12.7 kV SiC SICGT (SiC commutated gate turn-off thyristor) was developed for on-line uses in power utility applications, which has the highest blocking voltage among the reported semiconductor switching devices. Its leakage current is low and is less than 1/spl times/10/sup -3/ A/cm/sup 2/ at 9 kV and at 250/spl deg/C. Its on-state voltage at 100 A/cm/sup 2/ is 6.6 V and is lower than that of a 9 kV Si GTO, which is composed of two 4.5 kV GTOs connected in series. Its turn-on time and turn-off time are 0.22 /spl mu/s and 2.68 /spl mu/s respectively, which are about 1/50 and 1/10 of a commercialized 6 kV 6 kA Si-GTO. A PWM half bridge inverter composed of SICGTs demonstrated an output voltage of /spl plusmn/1.25 kV and output power of 0.8 kVA respectively, which are the highest values among the reported SiC half bridge inverters.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116156513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A novel fully self-aligned process for high cell density trench gate power MOSFETs 一种新型的高密度沟槽栅功率mosfet全自对准工艺
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239932
B. Tsui, T. Gan, Ming-da Wu, Hui-Hua Chou, Zhi-Liang Wu, C. Sune
{"title":"A novel fully self-aligned process for high cell density trench gate power MOSFETs","authors":"B. Tsui, T. Gan, Ming-da Wu, Hui-Hua Chou, Zhi-Liang Wu, C. Sune","doi":"10.1109/WCT.2004.239932","DOIUrl":"https://doi.org/10.1109/WCT.2004.239932","url":null,"abstract":"A novel self-aligned process for high cell density trench gate power MOSFETs with only four mask layers was proposed. The specific on-resistance can be as low as 0.21 m/spl Omega/.cm/sup 2/ With 1.5 /spl mu/m cell pitch and 35 V breakdown voltage. Because this process shrinks trench space but not trench width, the quasi-saturation phenomenon is lighter. After optimization of the thickness of n- drift layer and n+ substrate, a specific on-resistance lower than 0.1 m/spl Omega/.cm/sup 2/ with 0.6 /spl mu/m technology could be expected.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116768852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transient analysis of 3.3kV double-side double-gate IGBTs 3.3kV双面双栅igbt暂态分析
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239986
K. Hobart, F. Kub, M. Ancona, J. Neilson, P. Waind
{"title":"Transient analysis of 3.3kV double-side double-gate IGBTs","authors":"K. Hobart, F. Kub, M. Ancona, J. Neilson, P. Waind","doi":"10.1109/WCT.2004.239986","DOIUrl":"https://doi.org/10.1109/WCT.2004.239986","url":null,"abstract":"The transient behavior of double-side, double-gate IGBTs (DIGBTs) is presented. Devices fabricated with and without n-buffer layers are compared to conventional IGBTs. Both DIGBT designs show improved E/sub OFF/ and V/sub CE,ON/ compared with the 3.3 kV IGBTs. The improvement in V/sub CE,ON/ is 35% and 46% for devices with and without n-buffer layers, respectively, compared to conventional IGBTs. Improvement in turn-off loss is nearly 80%, achieving E/sub OFF/ as low as 9 mJ turning off 50 A at 1800 V.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123797592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An ultra-small isolation area for 600V class reverse blocking IGBT with deep trench isolation process (TI-RB-IGBT) 采用深沟槽隔离工艺的600V级反向阻断IGBT超小隔离区(TI-RB-IGBT)
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239843
N. Tokuda, M. Kaneda, T. Minato
{"title":"An ultra-small isolation area for 600V class reverse blocking IGBT with deep trench isolation process (TI-RB-IGBT)","authors":"N. Tokuda, M. Kaneda, T. Minato","doi":"10.1109/WCT.2004.239843","DOIUrl":"https://doi.org/10.1109/WCT.2004.239843","url":null,"abstract":"We developed a 600 V class trench isolation RB-IGBT (TI-RB-IGBT), whose termination area is extremely small in comparison with other isolation techniques, such as diffusion isolation or silicon mesa etching. The TI area is not only very small but also almost identical for all the blocking voltage classes. Our fabricated 100 A class TI-RB-IGBT, with one micron rule planar gate structure, has more than 600 V blocking capability for both directions, and its trade-off relationship between the forward voltage drop Vce(sat) and the turn-off energy loss Eoff is slightly better than our previous punch through (PT) type third generation planar gated IGBT, even though it has an n-body and the backside collector structure is of the NPT type.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125244962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
1200V reverse conducting IGBT 1200V反导IGBT
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239844
Hideki Takahashi, Aya Yamamoto, S. Aono, Tadaharu Minato
{"title":"1200V reverse conducting IGBT","authors":"Hideki Takahashi, Aya Yamamoto, S. Aono, Tadaharu Minato","doi":"10.1109/WCT.2004.239844","DOIUrl":"https://doi.org/10.1109/WCT.2004.239844","url":null,"abstract":"This report is the first to present the newly developed 1200 V reverse conducting IGBT (RC-IGBT) manufactured by using our thin wafer process technology. The fabricated RC-IGBT operates as both IGBT and free wheeling diode (FWD). Adopting a helium-irradiation carrier lifetime controlling technology to our RC-IGBT, the essential characteristics of the fabricated 1200 V/100 A chip can achieve a level comparable to those of conventional 3rd generation PT-type IGBT and FWD pair. The trade off with Vce(sat) and turn-off loss and the correlation between Vf and Err is almost the same as the conventional 3rd generation PT-type IGBT and FWD pair.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125471067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
AC/DC flyback converter with synchronous rectification 同步整流的交/直流反激变换器
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239752
F. Librizzi
{"title":"AC/DC flyback converter with synchronous rectification","authors":"F. Librizzi","doi":"10.1109/WCT.2004.239752","DOIUrl":"https://doi.org/10.1109/WCT.2004.239752","url":null,"abstract":"The design of a 70 W AC-DC converter is presented. The design is intended to achieve a good performance in terms of efficiency. This performance is reached using a quasi-resonant topology together with synchronous rectification on the secondary side. Comparisons between theoretical and experimental results are presented. The converter meets the no-load power consumption requirements indicated by the EU code of conduct.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124215905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Enhanced short-circuit withstanding capability of the emitter switched thyristor (EST) by employing a new protection circuit 采用一种新的保护电路，提高了发射极开关晶闸管的抗短路能力
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239987
B. Jeon, I. Ji, Soo-Seong Kim, Seung-Chul Lee, Yearn-Ik Choi, M. Han
{"title":"Enhanced short-circuit withstanding capability of the emitter switched thyristor (EST) by employing a new protection circuit","authors":"B. Jeon, I. Ji, Soo-Seong Kim, Seung-Chul Lee, Yearn-Ik Choi, M. Han","doi":"10.1109/WCT.2004.239987","DOIUrl":"https://doi.org/10.1109/WCT.2004.239987","url":null,"abstract":"A new protection circuit, which improves the short-circuit withstanding capability of an emitter switched thyristor (EST) is proposed and fabricated. Experimental results show that the EST employing the protection circuit exhibits a high voltage current saturation when the protection circuit reduces the gate voltage. We have also investigated the mechanism by employing two-dimensional simulation.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127974388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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