一种新型的高密度沟槽栅功率mosfet全自对准工艺

2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI:10.1109/WCT.2004.239932

B. Tsui, T. Gan, Ming-da Wu, Hui-Hua Chou, Zhi-Liang Wu, C. Sune

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引用次数: 1

摘要

提出了一种用于高密度槽栅功率mosfet的新型自对准工艺。比导通电阻可低至0.21 m/spl ω /。电池间距1.5 /spl μ /m，击穿电压35v。由于这一过程缩小了沟槽空间，但没有缩小沟槽宽度，因此准饱和现象较轻。优化n漂移层和n+衬底厚度后，比导通电阻小于0.1 m/spl ω /。0.6 /亩/亩技术可达到Cm /sup 2/ m2。

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A novel fully self-aligned process for high cell density trench gate power MOSFETs

A novel self-aligned process for high cell density trench gate power MOSFETs with only four mask layers was proposed. The specific on-resistance can be as low as 0.21 m/spl Omega/.cm/sup 2/ With 1.5 /spl mu/m cell pitch and 35 V breakdown voltage. Because this process shrinks trench space but not trench width, the quasi-saturation phenomenon is lighter. After optimization of the thickness of n- drift layer and n+ substrate, a specific on-resistance lower than 0.1 m/spl Omega/.cm/sup 2/ with 0.6 /spl mu/m technology could be expected.

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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs

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