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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs最新文献

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A 600V HVIC process with a built-in EPROM which enables new concept gate driving 内置EPROM的600V HVIC工艺，可实现新概念栅极驱动
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240218
K. Shimizu, S. Rittaku, J. Moritani
{"title":"A 600V HVIC process with a built-in EPROM which enables new concept gate driving","authors":"K. Shimizu, S. Rittaku, J. Moritani","doi":"10.1109/WCT.2004.240218","DOIUrl":"https://doi.org/10.1109/WCT.2004.240218","url":null,"abstract":"A junction isolation type 600 V HVIC process, which can produce EPROM memory devices, is developed for the first time. In this process, the 0.8 /spl mu/m CMOS design rule is applied and it is 20% finer than previous work. A new concept gate driver can be realized with a digital trimming circuit, in which dead-time control is possible. The trial fabrication devices exhibit compatible characteristics for the 0.8 /spl mu/m CMOS and EPROM. The modified-MFFP (multiple floating field plate) structure with GSR (ground-coupled shield ring) is applied to 600 V Nch/PchMOSs for level shift circuits, and as a result of reduction of the influence of the electric field from the level shift wiring, each device exhibits a high breakdown voltage beyond 700 V.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115148177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Investigation of VRM controllers [voltage regulator module] VRM控制器[稳压模块]研究
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239749
Xin Zhang, A. Huang
{"title":"Investigation of VRM controllers [voltage regulator module]","authors":"Xin Zhang, A. Huang","doi":"10.1109/WCT.2004.239749","DOIUrl":"https://doi.org/10.1109/WCT.2004.239749","url":null,"abstract":"This paper provides a systemic review of today's VRM controller architecture. The top-level building blocks of all known controllers are identified and they are the modulator, the compensator and the sensor. Novel concepts are then developed in these three areas for developing a high frequency, multiphase VRM controller.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115315935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Ultra-low on-resistance 60-100 V superjunction UMOSFETs fabricated by multiple ion-implantation 多离子注入制备超低导通电阻60-100 V超结umosfet
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239900
H. Ninomiya, Y. Miura, K. Kobayashi
{"title":"Ultra-low on-resistance 60-100 V superjunction UMOSFETs fabricated by multiple ion-implantation","authors":"H. Ninomiya, Y. Miura, K. Kobayashi","doi":"10.1109/WCT.2004.239900","DOIUrl":"https://doi.org/10.1109/WCT.2004.239900","url":null,"abstract":"We propose new low-voltage UMOSFETs with superjunction (SJ) structures to achieve ultra-low on-resistance. The present SJ structure has been formed by multiple boron ion implantations with varied energies up to 2 MeV. This technique enabled us to obtain p-columns with flat sidewalls, which minimize the interference to the drift conduction. The SJ diodes have clearly indicated the breakdown voltage enhancement, as expected, from the SJ characteristics. Drastic on-resistance reduction was demonstrated for the SJ-UMOSFETs with a breakdown voltage of 78 V.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115408690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A new vertical GaN Schottky barrier diode with floating metal ring for high breakdown voltage 一种新型高击穿电压悬浮金属环垂直GaN肖特基势垒二极管
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240037
Seung-Chul Lee, J. Her, Soo-Seong Kim, M. Ha, K. Seo, Yearn-Ik Choi, M. Han
{"title":"A new vertical GaN Schottky barrier diode with floating metal ring for high breakdown voltage","authors":"Seung-Chul Lee, J. Her, Soo-Seong Kim, M. Ha, K. Seo, Yearn-Ik Choi, M. Han","doi":"10.1109/WCT.2004.240037","DOIUrl":"https://doi.org/10.1109/WCT.2004.240037","url":null,"abstract":"A vertical GaN Schottky barrier diode (SBD) employing a floating metal ring as an edge termination is described. The breakdown voltage is larger than a device without any termination that has been fabricated on a bulk GaN substrate. Fabricated GaN SBD exhibits a high breakdown voltage of 353 V and very fast reverse recovery characteristics of 28 ns. The breakdown voltage of a device without termination is 159 V. It should be noted that the proposed device does not require any additional processes.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121352134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A monolithic electronic driver for fluorescent lamps 荧光灯的单片电子驱动器
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240041
A. L. La Barbera, V. Randazzo, S. Sueri, A. Russo, G. Distefano
{"title":"A monolithic electronic driver for fluorescent lamps","authors":"A. L. La Barbera, V. Randazzo, S. Sueri, A. Russo, G. Distefano","doi":"10.1109/WCT.2004.240041","DOIUrl":"https://doi.org/10.1109/WCT.2004.240041","url":null,"abstract":"This paper presents how the VIPower/sup /spl reg// M 3-3 STMiroelectronics proprietary technology is suitable to make \"smart\" power devices to drive fluorescent lamps. This technology integrates in the same chip a vertical flow power stage and a BCD based control circuit. The power stage consists of a high voltage bipolar transistor together with a low voltage n-channel MOS transistor in emitter switching configuration. The monolithic approach and the high level of integration well fit the application needs in terms of space saving (board miniaturization) and enhanced performance. An application board designed for FL tube driving is presented.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129825365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compact IPMs in transfer mold packages for low-power-motor drives 用于低功率电机驱动器的传输模具封装中的紧凑ipm
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240144
G. Majumdar, M. Iwasaki, M. Fukunaga, X. Kong
{"title":"Compact IPMs in transfer mold packages for low-power-motor drives","authors":"G. Majumdar, M. Iwasaki, M. Fukunaga, X. Kong","doi":"10.1109/WCT.2004.240144","DOIUrl":"https://doi.org/10.1109/WCT.2004.240144","url":null,"abstract":"This paper presents an excellent power module family for low power motor drives. The DIP-IPM (dual in-line package intelligent power module), with its transfer-mold packaging concept, is the most popular device, especially in today's consumer inverter market, for its cost-effective performance and high reliability. In this paper, the features of this kind of IPM and the background technologies supporting this successful device family are described.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128347664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
30V sub-micron shallow junction planar-MOSFET for DC-DC converters 用于DC-DC变换器的30V亚微米浅结平面mosfet
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240291
S. Ono, Y. Yamaguchi, Y. Kawaguchi, A. Nakagawa
{"title":"30V sub-micron shallow junction planar-MOSFET for DC-DC converters","authors":"S. Ono, Y. Yamaguchi, Y. Kawaguchi, A. Nakagawa","doi":"10.1109/WCT.2004.240291","DOIUrl":"https://doi.org/10.1109/WCT.2004.240291","url":null,"abstract":"We present sub-micron shallow p-base planar-DMOSFETs (DMOS: double diffused MOSFET type) for DC-DC converter applications. The shallow junction depth is quite useful to reduce the device on-resistance. It was found that the gate-drain feedback charge can effectively be reduced by adopting a very narrow and shallow JFET region with very high JFET donor concentration, based on the charge compensation theory. An experimental planar DMOSFET with p-base depth of 0.8 /spl mu/m exhibited a breakdown voltage of 34 V, an Ron*Qgd of 14.9 m/spl Omega/nC, and good UIS capability. This is the best value ever reported for a 30 V planar DMOSFET structure.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"94 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128699191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Field-plate effects on the breakdown voltage of an integrated high-voltage LDMOS transistor 场极板对集成高压LDMOS晶体管击穿电压的影响
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239969
Z. Hossain, T. Ishigwo, L. Tu, H. Corleto, F. Kuramae, R. Nair
{"title":"Field-plate effects on the breakdown voltage of an integrated high-voltage LDMOS transistor","authors":"Z. Hossain, T. Ishigwo, L. Tu, H. Corleto, F. Kuramae, R. Nair","doi":"10.1109/WCT.2004.239969","DOIUrl":"https://doi.org/10.1109/WCT.2004.239969","url":null,"abstract":"A 700 V double-resurf LDMOS (DR-LDMOS) with double-metal field plates is successfully integrated monolithically in a 1 /spl mu/ double-level metal (DLM) Bi-CMOS process for use in HV off-line switching applications. The process and device parameters, which determine the best-in-class specific on-resistance of lower than 200 mohm-cm/sup 2/, and a robust breakdown voltage of greater than 700 V, were optimized and addressed in our 1/sup st/ generation DR-LDMOS with single-level metal (SLM) process. It is found, during the DLM process development, that breakdown voltage begins to show significant degradation after stress when a 2/sup nd/ layer of dielectric layer (ILD-1) is added on top of Metal-1, as opposed to no degradation when there was no ILD-1 on top of Metal-1. This paper presents the re-optimization of DR-LDMOS with new Metal-2 field plate designs with respect to Metal-1 and ILD-1 to maintain a stable and robust breakdown voltage (BV) after stress.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129047913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
High-voltage 4H-SiC PiN rectifiers with single-implant, multi-zone JTE termination 高压4H-SiC引脚整流器，单植入，多区域JTE终端
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240032
P. Losee, S. Balachandran, L. Zhu, C. Li, J. Seiler, T. Chow, I. Bhat, R. Gutmann
{"title":"High-voltage 4H-SiC PiN rectifiers with single-implant, multi-zone JTE termination","authors":"P. Losee, S. Balachandran, L. Zhu, C. Li, J. Seiler, T. Chow, I. Bhat, R. Gutmann","doi":"10.1109/WCT.2004.240032","DOIUrl":"https://doi.org/10.1109/WCT.2004.240032","url":null,"abstract":"A novel multi-zone junction termination extension (MZJTE) is presented for high-voltage 4H-SiC pin junction rectifiers. Unlike the conventional multi-implantation or SiC etching approaches, our new termination technique utilizes multiple masking oxide etching steps to achieve a single-implant MZJTE structure that maintains surface planarity. Numerical device simulations have been performed to examine the process sensitivities, compared to single-zone JTE, and yielded breakdown voltages close to 90% of the ideal parallel-plane breakdown voltage. High voltage (V/sub BR//spl ap/8 kV) rectifiers were fabricated and experimental characteristics have been measured.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
IPMs solving major reliability issues in automotive applications [intelligent power module] ipm解决汽车应用中的主要可靠性问题[智能电源模块]
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239810
K. Hussein, G. Majurndar, S. Yoshida, H. Maekawa
{"title":"IPMs solving major reliability issues in automotive applications [intelligent power module]","authors":"K. Hussein, G. Majurndar, S. Yoshida, H. Maekawa","doi":"10.1109/WCT.2004.239810","DOIUrl":"https://doi.org/10.1109/WCT.2004.239810","url":null,"abstract":"In automotive applications, particularly the newly emerging hybrid electric vehicles (HEV), the high power ratings (10-100 kW peak), together with the high temperature associated with the engine room, subject the IPM (intelligent power module) to severe thermal operating conditions. Therefore, in addition to the well known requirements of improved IPM electrical characteristics and optimized system cost-performance (functional integration), reliability and durability become very important factors in HEV applications. This paper highlights the IPM system model for HEV: the intelligent integrated power drive unit (IPU) which, through efficient power chips, built-in detection, protection, and optimized package layout, pushes forward more functional integration and satisfies the HEV reliability requirements. The IPU thermal management (in terms of package layout and on-chip temperature sensing) and short-circuit protection circuits are introduced as examples.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124170614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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