A 600V HVIC process with a built-in EPROM which enables new concept gate driving

A junction isolation type 600 V HVIC process, which can produce EPROM memory devices, is developed for the first time. In this process, the 0.8 /spl mu/m CMOS design rule is applied and it is 20% finer than previous work. A new concept gate driver can be realized with a digital trimming circuit, in which dead-time control is possible. The trial fabrication devices exhibit compatible characteristics for the 0.8 /spl mu/m CMOS and EPROM. The modified-MFFP (multiple floating field plate) structure with GSR (ground-coupled shield ring) is applied to 600 V Nch/PchMOSs for level shift circuits, and as a result of reduction of the influence of the electric field from the level shift wiring, each device exhibits a high breakdown voltage beyond 700 V.