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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs最新文献

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Class D digital power amp (PurePath Digital/spl trade/) high Q musical content D类数字功放(PurePath digital /spl trade/)高Q音乐内容
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239812
C. Neesgaard, R. Antley, T. Efland, C. Kaya, K. Mochizuki, F. Nyboe, L. Risbo, D. Skelton, S. Unnikirishnan, A. Zhao
{"title":"Class D digital power amp (PurePath Digital/spl trade/) high Q musical content","authors":"C. Neesgaard, R. Antley, T. Efland, C. Kaya, K. Mochizuki, F. Nyboe, L. Risbo, D. Skelton, S. Unnikirishnan, A. Zhao","doi":"10.1109/WCT.2004.239812","DOIUrl":"https://doi.org/10.1109/WCT.2004.239812","url":null,"abstract":"The complex aspects of digital class D audio amplification and related technology issues are discussed. The focus is on a 100 W into 4 /spl Omega/ bridge-tied-load (BTL) power stage PIC. A 0.35 /spl mu/m BCD technology (LBC5) having 50 V LDMOS, and 10 /spl mu/m plated CuNiPd power metal, with bonding capability, was used to fabricate the chip.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131797027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
4H-SiC pin diodes on the (000-1) C-face with reduced forward degradation (000-1) c面上的4H-SiC引脚二极管，正向降解减少
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240153
K. Nakayama, Y. Sugawara, H. Tsuchida, Toshiyuki Miyanagi, I. Kamata, T. Nakamura, K. Asano, D. Takayama
{"title":"4H-SiC pin diodes on the (000-1) C-face with reduced forward degradation","authors":"K. Nakayama, Y. Sugawara, H. Tsuchida, Toshiyuki Miyanagi, I. Kamata, T. Nakamura, K. Asano, D. Takayama","doi":"10.1109/WCT.2004.240153","DOIUrl":"https://doi.org/10.1109/WCT.2004.240153","url":null,"abstract":"The dependence of a pin diode's forward voltage degradation on device structures and crystal faces has been investigated. This investigation clarified for the first time that forward voltage degradation is reduced by fabricating the diodes on the (000-1) C-face off-angled toward <11-20>. High voltage 4H-SiC pin diodes on the (000-1) C-face with reduced forward degradation have also been fabricated successfully. A pin diode's highest breakdown voltage of 4.6 kV is achieved, and /spl Delta/V/sub f/ reduces to 0.04 V.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new compact high dI/dt gate drive unit for 6-inch GCTs [gate commutated turn-off thyristor] 用于6英寸栅极整流关断晶闸管的新型紧凑型高dI/dt栅极驱动单元
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239984
H. Gruening, K. Koyanagi
{"title":"A new compact high dI/dt gate drive unit for 6-inch GCTs [gate commutated turn-off thyristor]","authors":"H. Gruening, K. Koyanagi","doi":"10.1109/WCT.2004.239984","DOIUrl":"https://doi.org/10.1109/WCT.2004.239984","url":null,"abstract":"A gate driver applying a ring of ceramic chip capacitors and MOSFETs around a GCT is presented, achieving unprecedented circular homogeneity of gate turn-off current and gate dI/dt-capability (>35kA//spl mu/s). A fast charger is added to reset the capacitor's voltage within less than 150 /spl mu/s after every GCT turn-off process. The turn-off current capability of 6 kV 6-inch asymmetric GCTs and 6 kV 6-inch reverse conducting GCTs is investigated with the new gate driver and compared to that achieved under traditional gate drive. Turnoff current capability improvement by x is observed with the new gate driver, wherein 18%","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115676638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
1200V FS-IGBT module with enhanced dynamic clamping capability 1200V FS-IGBT模块，增强动态夹紧能力
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240147
M. Otsuki, Y. Onozawa, S. Yoshiwatari, Y. Seki
{"title":"1200V FS-IGBT module with enhanced dynamic clamping capability","authors":"M. Otsuki, Y. Onozawa, S. Yoshiwatari, Y. Seki","doi":"10.1109/WCT.2004.240147","DOIUrl":"https://doi.org/10.1109/WCT.2004.240147","url":null,"abstract":"This paper describes the design concept to realize IGBT modules with large surge capability without any protection, such as gate controlled soft-turn-off and/or gate clamping zeners, especially focused on the large capacity fast switching FS (field-stop) IGBT modules. A 1200 V 450 A trench FS-IGBT module, which is designed to have optimum clamping voltage, has been able to obtain 6 /spl mu/sec-long UIS clamping turn off capability from two times larger current than its rating. Furthermore, the device survived after a 10 /spl mu/sec short-circuit followed by 2.5 /spl mu/sec clamping.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123660829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Impact of digital control in power electronics 数字控制对电力电子的影响
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240284
D. Maksimović, R. Zane, R. Erickson
{"title":"Impact of digital control in power electronics","authors":"D. Maksimović, R. Zane, R. Erickson","doi":"10.1109/WCT.2004.240284","DOIUrl":"https://doi.org/10.1109/WCT.2004.240284","url":null,"abstract":"In this paper, we discuss the impact of digital control in high-frequency switched-mode power supplies (SMPS), including point-of-load and isolated DC-DC converters, microprocessor power supplies, power-factor-correction rectifiers, electronic ballasts, etc., where switching frequencies are typically in the hundreds of kHz to MHz range, and where high efficiency, static and dynamic regulation, low size and weight, as well as low controller complexity and cost are very important. To meet these application requirements, a digital SMPS controller may include fast, small analog-to-digital converters, hardware-accelerated programmable compensators, programmable digital modulators with very fine time resolution, and a standard microcontroller core to perform programming, monitoring and other system interface tasks. Based on recent advances in circuit and control techniques, together with rapid advances in digital VLSI technology, we conclude that high-performance digital controller solutions are both feasible and practical, leading to much enhanced system integration and performance gains. Examples of experimentally demonstrated results are presented, together with pointers to areas of current and future research and development.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124471387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 430
Multi-voltage SOI-BiCDMOS for 14V&42V automotive applications 多电压SOI-BiCDMOS，用于14v和42v汽车应用
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239874
F. Kawai, T. Onishi, T. Kamiya, H. Ishimabushi, H. Eguchi, K. Nakaharna, H. Aoki, K. Hamada
{"title":"Multi-voltage SOI-BiCDMOS for 14V&42V automotive applications","authors":"F. Kawai, T. Onishi, T. Kamiya, H. Ishimabushi, H. Eguchi, K. Nakaharna, H. Aoki, K. Hamada","doi":"10.1109/WCT.2004.239874","DOIUrl":"https://doi.org/10.1109/WCT.2004.239874","url":null,"abstract":"This paper presents a new multi-voltage SOI-BiCDMOS, which particularly focuses on \"power MOSFET and BJT rich automotive applications\". This technology can integrate Nch LDMOS and Pch LDMOS which have 35 V/60 V/80 V breakdown voltages, high packing density deep trench isolated BJTs, and a low cost 0.8 /spl mu/m CMOS, on a single chip. The six types of LDMOS can be simultaneously fabricated with only two additional masks to a CMOS process, and these LDMOSs satisfy both low specific on-resistance and good SOA. Furthermore, in this technology, a bonded SOI wafer with 200 mm diameter has been newly adopted in order to reduce chip cost.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128220146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Over 55kV//spl mu/s, dv/dt turn-off characteristics of 4kV-static induction thyristor for pulsed power applications 用于脉冲功率应用的4kv静态感应晶闸管在55kV//spl μ /s以上，dv/dt关断特性
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239988
N. Shimizua, T. Sekiya, K. Iida, Y. Imanishi, M. Kimura, J. Nishizawa
{"title":"Over 55kV//spl mu/s, dv/dt turn-off characteristics of 4kV-static induction thyristor for pulsed power applications","authors":"N. Shimizua, T. Sekiya, K. Iida, Y. Imanishi, M. Kimura, J. Nishizawa","doi":"10.1109/WCT.2004.239988","DOIUrl":"https://doi.org/10.1109/WCT.2004.239988","url":null,"abstract":"Over 55 kV//spl mu/s, high voltage rise-up rated pulses have been successfully applied between the anode and the cathode of a 4 kV/300 A static induction thyristor (SIThy) during turn-off actions by applying the induction energy storage (IES) circuit invented in 2002 (K. Iida et al., 15th Symp. of Static Induction Devices, SSID-02-9, p.45-50, 2002). SIThys were destroyed when the high dv/dt value, over 2 kV//spl mu/s, was applied in the forward direction between the anode and the cathode during the turn-off action, by the conventional opening switching technique. We simulated the electric field strength inside of the SIThy on the IES circuit; consequently the electric field applied in front of the n-emitter during the turn-off action is absolutely low. This is considered to be the reason of the high tolerance for \"turn-off dv/dt\" of SIThys using the IES circuit.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121302215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
New 3300V chip generation with a trench IGBT and an optimized field stop concept with a smooth switching behavior 新的3300V芯片一代，具有沟槽IGBT和优化的场停止概念，具有平滑的开关行为
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239836
A. Pfaffenlehner, J. Biermann, C. Schaeffer, H. Schulze
{"title":"New 3300V chip generation with a trench IGBT and an optimized field stop concept with a smooth switching behavior","authors":"A. Pfaffenlehner, J. Biermann, C. Schaeffer, H. Schulze","doi":"10.1109/WCT.2004.239836","DOIUrl":"https://doi.org/10.1109/WCT.2004.239836","url":null,"abstract":"IGBT3 technology, with its trench cell and field stop is introduced for high voltage applications. The field stop concept has to be optimized, if modules with a high rated current are used in applications with a high stray inductance, to ensure the controllability of the voltage overshoot. The realized devices have greatly reduced losses in typical applications and allow an increase of the power output of converters.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121345541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A new GaN based field effect Schottky barrier diode with a very low on-voltage operation 一种基于GaN的场效应肖特基势垒二极管，具有极低的导通电压
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240038
S. Yoshida, N. Ikeda, J. Li, T. Wada, H. Takehara
{"title":"A new GaN based field effect Schottky barrier diode with a very low on-voltage operation","authors":"S. Yoshida, N. Ikeda, J. Li, T. Wada, H. Takehara","doi":"10.1109/WCT.2004.240038","DOIUrl":"https://doi.org/10.1109/WCT.2004.240038","url":null,"abstract":"We first demonstrated a new structure of GaN Schottky diode, with dual Schottky structures. That is, a field effect Schottky barrier diode (FESBD) was fabricated. The purpose of this diode was to lower the on-state voltage and to maintain a high reverse breakdown voltage. This diode was fabricated using an AlGaN/GaN heterojunction and a selective area growth (SAG) technique. We obtained an on-state voltage below 0.1 V, using a vertical type FESBD and the breakdown voltage was over 400 V using a planar type FESBD.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121555496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A multi trench analog+logic protection (M-TRAP) for substrate crosstalk prevention in a 0.25 /spl mu/m smart power platform with 100V high-side capability 一种多沟道模拟+逻辑保护(m - trap)，用于在0.25 /spl mu/m具有100V高侧能力的智能电源平台中防止衬底串扰
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240347
V. Parthasarathy, V. Khemka, R. Zhu, I. Puchades, T. Roggenbauer, M. Butner, P. Hui, P. Rodriquez, A. Bose
{"title":"A multi trench analog+logic protection (M-TRAP) for substrate crosstalk prevention in a 0.25 /spl mu/m smart power platform with 100V high-side capability","authors":"V. Parthasarathy, V. Khemka, R. Zhu, I. Puchades, T. Roggenbauer, M. Butner, P. Hui, P. Rodriquez, A. Bose","doi":"10.1109/WCT.2004.240347","DOIUrl":"https://doi.org/10.1109/WCT.2004.240347","url":null,"abstract":"We have previously reported a 74 V (typical) high-side capable 0.25 /spl mu/m smart power technology with deep trench and a thick p-epi on P++ substrate (V. Parthasarathy et al, IEDM, p.459-462, 2002). A unique trade-off between high-side capability and substrate injection protection in a power IC process was identified and discussed. In this paper, we reveal a key technology enabler on this platform: an isolation structure which utilizes a series of deep trenches with fixed width outside the power device as a physical barrier to redirect electron flow into a more heavily doped region with low lifetime. We have exploited this technique to realize a parasitic collection current of less than 100 nA for an injected NLDMOS negative drain current of 3 A in a distance of less than 30 /spl mu/m without any guard ring biasing scheme. The high side capability of this platform has been upgraded to 100 V (typical) through innovative device and layout design and without any process modification.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123796155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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