F. Kawai, T. Onishi, T. Kamiya, H. Ishimabushi, H. Eguchi, K. Nakaharna, H. Aoki, K. Hamada
{"title":"多电压SOI-BiCDMOS,用于14v和42v汽车应用","authors":"F. Kawai, T. Onishi, T. Kamiya, H. Ishimabushi, H. Eguchi, K. Nakaharna, H. Aoki, K. Hamada","doi":"10.1109/WCT.2004.239874","DOIUrl":null,"url":null,"abstract":"This paper presents a new multi-voltage SOI-BiCDMOS, which particularly focuses on \"power MOSFET and BJT rich automotive applications\". This technology can integrate Nch LDMOS and Pch LDMOS which have 35 V/60 V/80 V breakdown voltages, high packing density deep trench isolated BJTs, and a low cost 0.8 /spl mu/m CMOS, on a single chip. The six types of LDMOS can be simultaneously fabricated with only two additional masks to a CMOS process, and these LDMOSs satisfy both low specific on-resistance and good SOA. Furthermore, in this technology, a bonded SOI wafer with 200 mm diameter has been newly adopted in order to reduce chip cost.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Multi-voltage SOI-BiCDMOS for 14V&42V automotive applications\",\"authors\":\"F. Kawai, T. Onishi, T. Kamiya, H. Ishimabushi, H. Eguchi, K. Nakaharna, H. Aoki, K. Hamada\",\"doi\":\"10.1109/WCT.2004.239874\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new multi-voltage SOI-BiCDMOS, which particularly focuses on \\\"power MOSFET and BJT rich automotive applications\\\". This technology can integrate Nch LDMOS and Pch LDMOS which have 35 V/60 V/80 V breakdown voltages, high packing density deep trench isolated BJTs, and a low cost 0.8 /spl mu/m CMOS, on a single chip. The six types of LDMOS can be simultaneously fabricated with only two additional masks to a CMOS process, and these LDMOSs satisfy both low specific on-resistance and good SOA. Furthermore, in this technology, a bonded SOI wafer with 200 mm diameter has been newly adopted in order to reduce chip cost.\",\"PeriodicalId\":303825,\"journal\":{\"name\":\"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WCT.2004.239874\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WCT.2004.239874","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multi-voltage SOI-BiCDMOS for 14V&42V automotive applications
This paper presents a new multi-voltage SOI-BiCDMOS, which particularly focuses on "power MOSFET and BJT rich automotive applications". This technology can integrate Nch LDMOS and Pch LDMOS which have 35 V/60 V/80 V breakdown voltages, high packing density deep trench isolated BJTs, and a low cost 0.8 /spl mu/m CMOS, on a single chip. The six types of LDMOS can be simultaneously fabricated with only two additional masks to a CMOS process, and these LDMOSs satisfy both low specific on-resistance and good SOA. Furthermore, in this technology, a bonded SOI wafer with 200 mm diameter has been newly adopted in order to reduce chip cost.