V. Khemka, V. Parthasarathy, R. Zhu, A. Bose, T. Roggenbauer
{"title":"Floating RESURF (FRESURF) LDMOSFET devices with breakthrough BV/sub dss/-R/sub dson/ (for example: 47V - 0.28m/spl Omega/.cm/sup 2/ or 93V - 0.82 m/spl Omega/.cm/sup 2/)","authors":"V. Khemka, V. Parthasarathy, R. Zhu, A. Bose, T. Roggenbauer","doi":"10.1109/WCT.2004.240296","DOIUrl":"https://doi.org/10.1109/WCT.2004.240296","url":null,"abstract":"In this paper, we propose and demonstrate a novel device concept, which is an extension of the conventional reduced surface field (RESURF) concept. A heavily doped n-type floating region is introduced in the conventional lateral DMOSFET (LDMOS) device structure which allows the breakdown capability of the device to be increased significantly while at the same time making it high-side capable. This floating RESURF (FRESURF) device concept allows the realization of significantly higher breakdown voltage in a thin epitaxy based power IC technology. Several different LDMOS type device structures based on the FRESURF concept are proposed, simulated and experimentally demonstrated. Breakthrough BV/sub dss/-R/sub dson/A trade-off has been realized using this device, which can be fabricated in a conventional power IC technology without any added process complexity. BV/sub dss/-R/sub dson/A figures like 47 V 0.28m/spl Omega/.cm/sup 2/ or 93 V - 0.82 m/spl Omega/.cm/sup 2/ have been realized, which are best reported figures in the industry for this class of power device and on-par with some of the figures achieved using more complicated superjunction technology.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115333573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Sasaki, H. Takao, T. Shikano, S. Fujita, D. Nakajima, T. Shinohara
{"title":"Development of high current transfer-mold type power module with high heat-cycle durability [motor drive applications]","authors":"T. Sasaki, H. Takao, T. Shikano, S. Fujita, D. Nakajima, T. Shinohara","doi":"10.1109/WCT.2004.239991","DOIUrl":"https://doi.org/10.1109/WCT.2004.239991","url":null,"abstract":"High current transfer-molded type power modules have been developed for industrial motor drive systems. The key issue in this development was to improve the heat dissipation characteristics of the existing transfer-molded package construction. To achieve this, a new concept of directly soldering power chips onto heat spreaders has been adopted. However, the strain on solder joints by heat-cycling stress became an issue in the development process. It has been solved by creating specially designed dimples on copper heat spreaders integrated in the structure and using a new resin, which has a linear expansion coefficient close to that of the metal. The durability of a new transfer molded type high-current power module, which has been developed based on the novel structural concept, has been ascertained by heat cycling and other tests. In this paper, the authors describe some major aspects of the new design and provide results of confirmatory tests performed on the device.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127610548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel ultra high voltage 4H-SiC bipolar device: MAGBT","authors":"K. Asano, Y. Sugawara, K. Nakayama","doi":"10.1109/WCT.2004.240033","DOIUrl":"https://doi.org/10.1109/WCT.2004.240033","url":null,"abstract":"A novel normally-off SiC MOS accumulated channel gate bipolar transistor, called MAGBT, with a high blocking voltage is proposed for high voltage applications. This MAGBT can be expected to realize a high blocking voltage and a low on-state voltage drop. Even if the blocking voltage is greater than 20 kV, the on-state voltage drop at 100 A/cm/sup 2/ can be expected to be less than 6.5 V. Furthermore, high safety against latch up can be expected.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131182853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takashi Kojima, Y. Yamada, M. Ciappa, Marco Chiavarini, Wolfgang Fichtner
{"title":"A novel electro-thermal simulation approach of power IGBT modules for automotive traction applications","authors":"Takashi Kojima, Y. Yamada, M. Ciappa, Marco Chiavarini, Wolfgang Fichtner","doi":"10.1109/WCT.2004.239990","DOIUrl":"https://doi.org/10.1109/WCT.2004.239990","url":null,"abstract":"In this paper, a novel thermal compact model of IGBT power modules for automotive applications is proposed. This new technique combines the accuracy of the FEM approach with the fast computational performances of circuit simulators. Furthermore, a simple parameter definition method for power device models, which enables us to change the device characteristics dynamically, is introduced. These methods provide an excellent tool to investigate issues such as the temperature non-homogeneity in parallel-connected devices.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114233358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Hattori, K. Nakashima, M. Kuwahara, T. Yoshida, S. Yamauchi, H. Yamaguchi
{"title":"Design of a 200V super junction MOSFET with n-buffer regions and its fabrication by trench filling","authors":"Y. Hattori, K. Nakashima, M. Kuwahara, T. Yoshida, S. Yamauchi, H. Yamaguchi","doi":"10.1109/WCT.2004.239903","DOIUrl":"https://doi.org/10.1109/WCT.2004.239903","url":null,"abstract":"A new super junction trench MOSFET, which has n-buffer regions between trench gates and n columns, was designed and demonstrated. In this structure, the specific on-resistance (R/sub ON/) does not increase as long as the trench gate bottom is covered with the n buffer, even though the gate position shifts from the designed one. The drift region, consisting of p/n columns in the structure, were formed by a trench filling epitaxial method. The fabricated SJ-MOSFET with a fine cell pitch of 4 /spl mu/m showed an RON of 2.3 n/spl Omega/.cm/sup 2/ at a breakdown voltage (V/sub BR/) of 203 V. The R/sub on/ is 35% lower than that of the silicon limit.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132487266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Inaba, J. Sakano, S. Shirakawa, H. Miyazaki, M. Iwamura, Y. Maeda, K. Mashino, Y. Nagai, M. Mori
{"title":"Sub-system power module for a 42V motor generator system [automotive applications]","authors":"M. Inaba, J. Sakano, S. Shirakawa, H. Miyazaki, M. Iwamura, Y. Maeda, K. Mashino, Y. Nagai, M. Mori","doi":"10.1109/WCT.2004.239867","DOIUrl":"https://doi.org/10.1109/WCT.2004.239867","url":null,"abstract":"We have developed an 80 V 500 A SSPM (sub-system power module) for a 42 V motor generator automotive system. The SSPM achieves high reliability using a low loss inverter with a low on-resistance (1.5 m/spl Omega/ typ.) trench power MOSFET, a low inductance (27 nH) power module, and a soft gate 3-phase driver IC with a newly developed active clamp method.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128998472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Nakagawa, T. Matsudai, T. Matsuda, M. Yamaguchi, T. Ogura
{"title":"MOSFET-mode ultra-thin wafer PTIGBTs for soft switching application $theory and experiments","authors":"A. Nakagawa, T. Matsudai, T. Matsuda, M. Yamaguchi, T. Ogura","doi":"10.1109/WCT.2004.239815","DOIUrl":"https://doi.org/10.1109/WCT.2004.239815","url":null,"abstract":"We have previously proposed and analyzed the MOSFET-mode operation of ultra-thin wafer PTIGBTs in (T. Matsudai et. al., Proc. of ISPSD'02, p.258). The present paper, for the first time, presents an analytical theory of MOSFET-mode operation, and shows that the safe operating area is determined by a mechanism similar to the second breakdown of npn bipolar transistors. The present paper also experimentally demonstrates, for the first time, that the MOSFET-mode IGBTs are strongly effective for soft switching applications. The developed MOSFET-mode 900 V 60 A thin wafer trench gate PTIGBTs have reduced turn-off loss by 55% at 125/spl deg/C, compared with the conventional (4th generation) soft switching PTIGBTs.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125175527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Narazaki, K. Takano, K. Oku, H. Hamachi, T. Minato
{"title":"A marvelous low on-resistance 20V rated self alignment trench MOSFET (SAT-MOS) in a 0.35/spl mu/m LSI design rule with both high forward blocking voltage yield and large current capability","authors":"A. Narazaki, K. Takano, K. Oku, H. Hamachi, T. Minato","doi":"10.1109/WCT.2004.240223","DOIUrl":"https://doi.org/10.1109/WCT.2004.240223","url":null,"abstract":"In this paper, we propose the SAT-MOS, which achieved marvelous performance of the specific on-resistance (Ron, sp): 6.5 m/spl Omega/mm/sup 2/ (@Vdss=30.8 V) by minimizing the unit cell pitch on a 0.35 /spl mu/m LSI design rule. This is the lowest value of 20 V rated MOSFETs ever been reported. The fabricated SAT-MOS Ron,sp ratio to the Si limit reaches the ultimate value of 208% in this voltage class. The SAT-MOS maintains an excellent Vdss uniformity on a wafer, because our proposed SAC (shallow trench contact) structure and procedure has a very large process window for SAC trench depth if the source contact trench depth disperses more than 20%. As a result, we could present the SAT-MOS, which has both a large current capability of over 100 A/mm/sup 2/ in a static forward bias condition and an avalanche ruggedness of over 25 A/mm/sup 2/ during unclamped inductive switching (UIS).","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130886015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of plasma extraction transit time oscillations in bipolar power devices","authors":"R. Siemieniec, P. Mourick, L. Josef, M. Netzel","doi":"10.1109/WCT.2004.239972","DOIUrl":"https://doi.org/10.1109/WCT.2004.239972","url":null,"abstract":"The occurrence of high-frequency PETT (plasma extraction transit time) oscillations is related to the transit-time of the carrier transport through the already formed space-charge region at the end of the turn-off process of bipolar power devices. These oscillations are found only in the case of a matching external LC circuit which acts as a resonance circuit. It is shown that the occurrence of this type of oscillation depends on a wide range of parameters. 3D EMC simulation is used for the estimation of resonance points of a complete power module.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134106926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Kawamoto, T. Tanaka, M. Kimata, T. Ohi, H. Yamaguchi
{"title":"Application of high voltage HVIPM in propulsion control of rail vehicles [intelligent power modules]","authors":"S. Kawamoto, T. Tanaka, M. Kimata, T. Ohi, H. Yamaguchi","doi":"10.1109/WCT.2004.239870","DOIUrl":"https://doi.org/10.1109/WCT.2004.239870","url":null,"abstract":"Intelligent power modules (HVIPMs) have been applied in propulsion controllers of rail vehicles for the past seven years, and the high voltage versions of these, called HVIPMs, are also in use for almost five years now. During this period, the HVIPMs came to be applied in a wide range of controllers from small capacity types (120 kW using 3300 V/1200 A rated HVIPMs in a 2-level configuration) for light vehicles to large capacity types (1200 kW using 3300 V/1200 A rated HVIPMs in a 3-level configuration) for 'Shinkansen' trains. In this paper, some design aspects of the latest HVIPMs, rated 3300 - 6500 V/600 - 1200 A, applied in the propulsion control of rail vehicles is introduced, including details of various system topologies developed so far and the progress achieved thereby. The paper discusses the power and circuit integration concept adopted in configuring this HVIPM family, detailing its power and control circuit functionalities and how such an integration concept has contributed in downsizing dimensions and enhancing reliability of the applied systems.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134562390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}