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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs最新文献

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Design of a monolithic low voltage high efficiency boost DC-DC converter ASIC based on 0.5/spl mu/m CMOS process 基于0.5/spl μ m CMOS工艺的单片低压高效升压DC-DC变换器ASIC的设计
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239875
Haifei Deng, N. Sun, Xiaoming Duan, Yan Ma, A. Huang, D. Chen
{"title":"Design of a monolithic low voltage high efficiency boost DC-DC converter ASIC based on 0.5/spl mu/m CMOS process","authors":"Haifei Deng, N. Sun, Xiaoming Duan, Yan Ma, A. Huang, D. Chen","doi":"10.1109/WCT.2004.239875","DOIUrl":"https://doi.org/10.1109/WCT.2004.239875","url":null,"abstract":"The earth is mobile. There is a huge market for mobile power today and in the future. Efficient performance, functionality, small profile and low cost are the most wanted features for mobile power management ICs. Compared with the discrete switching DC-DC converter, monolithic integration brings a lot of benefits and new design issues. In this work, a monolithic low voltage high efficiency step-up DC-DC converter for nickel metal hydride or alkaline battery powered applications is designed, based on a low voltage CMOS process. Several novel design concepts are proposed for compensator design, low voltage startup, light load efficiency and power device optimization.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130128512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ultra low on-resistance Super 3D MOSFET under 300 V breakdown voltage 超低导通电阻300v击穿电压下的超级3D MOSFET
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239933
J. Sakakibara, Y. Urakami, H. Yamaguchi
{"title":"Ultra low on-resistance Super 3D MOSFET under 300 V breakdown voltage","authors":"J. Sakakibara, Y. Urakami, H. Yamaguchi","doi":"10.1109/WCT.2004.239933","DOIUrl":"https://doi.org/10.1109/WCT.2004.239933","url":null,"abstract":"For the range of under 300 V breakdown voltage, we have already proposed a new structural power MOSFET that we call Super 3D MOSFET. At 70 V breakdown voltage, the simulated total specific on-resistance was 19 mohm.mm/sup 2/, and below the R/sub on/ Si limit. In this work, we present the structural design for the breakdown voltage, taking the electric field concentration into consideration at its 3-dimensional corner. Furthermore, we present the experimental results for an actual prototype fabrication. The on-resistance and breakdown voltage are respectively 27 mohm.mm/sup 2/ and 49 V. This on-resistance is reduced drastically in comparison with the conventional trench-gated MOSFET.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131542747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High density, low on-resistance, high side N-channel trench lateral power MOSFET with thick copper metal 高密度，低导通电阻，高边n沟道横向功率MOSFET与厚铜金属
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239899
M. Sawada, A. Sugi, M. Iwaya, K. Takagiwa, S. Matsunaga, S. Kajiwara, K. Mochizuki, N. Fujishima
{"title":"High density, low on-resistance, high side N-channel trench lateral power MOSFET with thick copper metal","authors":"M. Sawada, A. Sugi, M. Iwaya, K. Takagiwa, S. Matsunaga, S. Kajiwara, K. Mochizuki, N. Fujishima","doi":"10.1109/WCT.2004.239899","DOIUrl":"https://doi.org/10.1109/WCT.2004.239899","url":null,"abstract":"We proposed a low side N-channel trench lateral power MOSFET (TLPM) in (N.Fujishima et al, Proc. of IEDM 2002, p.455-458). In this paper, a high side N-channel TLPM, which is isolated from the substrate, is proposed, fabricated and characterized for the first time. The fabricated high side TLPM devices exhibit a specific on-resistance of 17 m/spl Omega/-mm/sup 2/ with a breakdown voltage of 21 V.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134219712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Mixed mode 3D pseudo-1chip ESD surge simulation using hydrodynamic model for new LDMOS cell layout realizing super high ESD endurance over 25kV/mm2 利用流体动力学模型对新型LDMOS电池布局进行混合模式三维伪芯片ESD浪涌仿真，实现超过25kV/mm2的超高ESD续航能力
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239745
K. Kohno, S. Takahashi, H. Himi, Y. Higuchi
{"title":"Mixed mode 3D pseudo-1chip ESD surge simulation using hydrodynamic model for new LDMOS cell layout realizing super high ESD endurance over 25kV/mm2","authors":"K. Kohno, S. Takahashi, H. Himi, Y. Higuchi","doi":"10.1109/WCT.2004.239745","DOIUrl":"https://doi.org/10.1109/WCT.2004.239745","url":null,"abstract":"For the first time, a new ESD surge simulation method that combines a 3D pseudo-1chip device model, consisting of an internal LDMOS cell and peripheral LDMOS cell, and a hydrodynamic physical model, is proposed in order to analyze the ESD destruction mechanism of LDMOS and optimize the cell layout against ESD. The simulation results show good agreement with experiments on ESD endurance and surge current crowding phenomena at the peripheral cell, causing poor ESD endurance. Utilizing the proposed simulation method, we developed a new LDMOS cell layout, achieving super high ESD endurance over 25 kV/mm/sup 2/.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114187446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Stacked BSCR ESD protection for 250V tolerant circuits 250V容限电路的堆叠式BSCR ESD保护
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239937
V. Vashchenko, A. Concannon, M. ter Beek, P. Hopper
{"title":"Stacked BSCR ESD protection for 250V tolerant circuits","authors":"V. Vashchenko, A. Concannon, M. ter Beek, P. Hopper","doi":"10.1109/WCT.2004.239937","DOIUrl":"https://doi.org/10.1109/WCT.2004.239937","url":null,"abstract":"A device level solution for on-chip ESD protection for high-voltage applications is reported. Using technology CAD, a new stacked bipolar-triggered SCR device architecture is proposed and further validated by experimental measurements in a 250 V complementary BJT process.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124474137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Physically based simulation of strong charge multiplication events in power devices triggered by incident ions 由入射离子触发的功率器件中强电荷倍增事件的物理模拟
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239974
W. Kaindl, G. Solkner, H. Becker, J. Meijer, H. Schulze, G. Wachutka
{"title":"Physically based simulation of strong charge multiplication events in power devices triggered by incident ions","authors":"W. Kaindl, G. Solkner, H. Becker, J. Meijer, H. Schulze, G. Wachutka","doi":"10.1109/WCT.2004.239974","DOIUrl":"https://doi.org/10.1109/WCT.2004.239974","url":null,"abstract":"Non-destructive ion irradiation experiments and corresponding device simulations were performed in order to investigate the radiation sensitivity of different device structures. We modeled an irradiation experiment in which a high power diode is exposed to /sup 84/Kr, /sup 28/Si, and /sup 12/C-ions in order to validate and calibrate the simulation models. Device simulations reveal spatial and temporal distributions of electric field and carrier densities occurring in the interior of the device. Therefore, they help to identify and explain the mechanism of strong charge multiplication induced by incident ions.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121736397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
1200V class reverse blocking IGBT (RB-IGBT) for AC matrix converter 用于交流矩阵变换器的1200V级反向阻断IGBT (RB-IGBT)
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239841
H. Takahashi, M. Kaneda, T. Minato
{"title":"1200V class reverse blocking IGBT (RB-IGBT) for AC matrix converter","authors":"H. Takahashi, M. Kaneda, T. Minato","doi":"10.1109/WCT.2004.239841","DOIUrl":"https://doi.org/10.1109/WCT.2004.239841","url":null,"abstract":"This paper presents a novel 1200 V RB-IGBT for an AC matrix converter. The 1200 V RB-IGBT is made by a deep diffusion isolation process and thin wafer process technology. Our fabricated RB-IGBT achieved more than 1200 V reverse blocking capability and the same forward voltage drop Vce(sat) and turn-off energy loss Eoff characteristics as our previous punch through type (PT-type) third generation IGBT. Therefore, it is possible to reduce the total loss in the AC matrix converter operation compared with the conventional IGBT and diode coupling.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122159445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A new collector structure for thin wafer NPT-IGBT with low dose p- Si injection layer and high dose p+ Ge contact layer 一种具有低剂量p- Si注入层和高剂量p+ Ge接触层的NPT-IGBT薄片集电极结构
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240352
T. Sugiyama, H. Ueda, M. Ishiko
{"title":"A new collector structure for thin wafer NPT-IGBT with low dose p- Si injection layer and high dose p+ Ge contact layer","authors":"T. Sugiyama, H. Ueda, M. Ishiko","doi":"10.1109/WCT.2004.240352","DOIUrl":"https://doi.org/10.1109/WCT.2004.240352","url":null,"abstract":"We have proposed a new collector structure for thin wafer IGBTs to improve contact resistances without sacrificing turnoff losses. The proposed structure has a low dose p- Si injection layer and a high dose p+ Ge contact. We also demonstrate, for the first time, the performance of 1.2 kV 200 A class thin wafer NPT IGBTs using this new collector structure. As a result, from simulations and measurements, we found that the high dose p+ Ge layer acts to suppress the hole-injection and also provides low contact resistances without consequently sacrificing turnoff losses.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122578410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The influence of body effect and threshold voltage reduction on trench MOSFET body diode characteristics 体效应和阈值降压对沟槽MOSFET体二极管特性的影响
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239935
G. Dolny, S. Sapp, A. Elbanhaway, C. F. Wheatley
{"title":"The influence of body effect and threshold voltage reduction on trench MOSFET body diode characteristics","authors":"G. Dolny, S. Sapp, A. Elbanhaway, C. F. Wheatley","doi":"10.1109/WCT.2004.239935","DOIUrl":"https://doi.org/10.1109/WCT.2004.239935","url":null,"abstract":"This paper presents a comprehensive study of the body diode characteristics of high-channel density trench power MOSFETs using analytic modeling, 2-dimensional numerical simulation, and physical measurements. The results show that, for state-of-the-art trench MOSFETs, the body diode characteristics are strongly influenced by majority carriers in the channel due to gate-controlled third quadrant conduction. This large channel current is shown to be the result of dynamic threshold voltage lowering due to the MOSFET body effect.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"9 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126101980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Recent progress in SiC bipolar junction transistors 碳化硅双极结晶体管的最新进展
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240154
A. K. Agarwa, S. Ryu, J. Richmond, C. Capell, J. Palmour, S. Balachandran, T. Chow, B. Geif, S. Bayne, C. Scozzie, K. Jones
{"title":"Recent progress in SiC bipolar junction transistors","authors":"A. K. Agarwa, S. Ryu, J. Richmond, C. Capell, J. Palmour, S. Balachandran, T. Chow, B. Geif, S. Bayne, C. Scozzie, K. Jones","doi":"10.1109/WCT.2004.240154","DOIUrl":"https://doi.org/10.1109/WCT.2004.240154","url":null,"abstract":"Bipolar junction transistors (BJT) and integrated Darlington pairs have been developed in 4H-SiC. The 3 mm x 3 mm BJTs show an on-state current of 20 A at a forward drop of 1.2 V at room temperature. The smaller 2 mm x 2 mm devices were tested up to 325 /spl deg/C. The on-resistance increases and the current gain reduces with increasing temperature. The reverse leakage current was measured to be less than 40 muA at 1000 V and 325 /spl deg/C. Inductive switching at 1000 V, 5 A shows extremely fast turn-on and turn-off behavior.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128490121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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