{"title":"P/sup -/外延/P/sup ++/衬底智能电源技术中寄生少数载流子电流的理解和抑制的新成果","authors":"R. Stella, S. Favilla, G. Croce","doi":"10.1109/WCT.2004.240346","DOIUrl":null,"url":null,"abstract":"In this paper, parasitic electron currents in P/sup -//P/sup ++/ substrates are thoroughly investigated by the results of numerical simulations, the predictions of an analytical model, and experiments. An optimization of the protection technique, which does not require the addition of a deep trench isolation, and allows similar results in the suppression of the parasitic currents, is proposed.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Novel achievements in the understanding and suppression of parasitic minority carrier currents in P/sup -/ epitaxy/P/sup ++/ substrate smart power technologies\",\"authors\":\"R. Stella, S. Favilla, G. Croce\",\"doi\":\"10.1109/WCT.2004.240346\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, parasitic electron currents in P/sup -//P/sup ++/ substrates are thoroughly investigated by the results of numerical simulations, the predictions of an analytical model, and experiments. An optimization of the protection technique, which does not require the addition of a deep trench isolation, and allows similar results in the suppression of the parasitic currents, is proposed.\",\"PeriodicalId\":303825,\"journal\":{\"name\":\"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WCT.2004.240346\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WCT.2004.240346","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel achievements in the understanding and suppression of parasitic minority carrier currents in P/sup -/ epitaxy/P/sup ++/ substrate smart power technologies
In this paper, parasitic electron currents in P/sup -//P/sup ++/ substrates are thoroughly investigated by the results of numerical simulations, the predictions of an analytical model, and experiments. An optimization of the protection technique, which does not require the addition of a deep trench isolation, and allows similar results in the suppression of the parasitic currents, is proposed.