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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs最新文献

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Optimization of integrated vertical DMOS transistors for ESD robustness 集成垂直DMOS晶体管ESD稳健性优化
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239936
P. Moens, K. Reynders, S. Bychikhin, D. Pogany, M. Zubeidat
{"title":"Optimization of integrated vertical DMOS transistors for ESD robustness","authors":"P. Moens, K. Reynders, S. Bychikhin, D. Pogany, M. Zubeidat","doi":"10.1109/WCT.2004.239936","DOIUrl":"https://doi.org/10.1109/WCT.2004.239936","url":null,"abstract":"This paper analyses the ESD robustness of vertically integrated DMOS transistors. The relation between the snapback current (I/sub sb/) and the device layout, and between the thermal failure current (I/sub tf/) and the buried layer process conditions is established. The physical mechanisms responsible for hot spot hopping between two adjacent vertical bipolars; are highlighted. Optimisation for ESD robustness means giving up on R/sub on/. The optimum process and layout conditions are determined.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130872039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Novel achievements in the understanding and suppression of parasitic minority carrier currents in P/sup -/ epitaxy/P/sup ++/ substrate smart power technologies P/sup -/外延/P/sup ++/衬底智能电源技术中寄生少数载流子电流的理解和抑制的新成果
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240346
R. Stella, S. Favilla, G. Croce
{"title":"Novel achievements in the understanding and suppression of parasitic minority carrier currents in P/sup -/ epitaxy/P/sup ++/ substrate smart power technologies","authors":"R. Stella, S. Favilla, G. Croce","doi":"10.1109/WCT.2004.240346","DOIUrl":"https://doi.org/10.1109/WCT.2004.240346","url":null,"abstract":"In this paper, parasitic electron currents in P/sup -//P/sup ++/ substrates are thoroughly investigated by the results of numerical simulations, the predictions of an analytical model, and experiments. An optimization of the protection technique, which does not require the addition of a deep trench isolation, and allows similar results in the suppression of the parasitic currents, is proposed.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121314656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A new sub-micron 24 V SiGe:C resurf HBT 一种新型亚微米24 V SiGe:C重燃HBT
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240289
J. Melai, P. Magnée, R. Hueting, F. Neuilly, R. de Kort, J. Slotboom
{"title":"A new sub-micron 24 V SiGe:C resurf HBT","authors":"J. Melai, P. Magnée, R. Hueting, F. Neuilly, R. de Kort, J. Slotboom","doi":"10.1109/WCT.2004.240289","DOIUrl":"https://doi.org/10.1109/WCT.2004.240289","url":null,"abstract":"For the first time a SiGe:C heterojunction bipolar transistor (HBT) is presented that uses the resurf effect to improve the cutoff frequency (f/sub T/) for a specified collector-base junction breakdown voltage (BV/sub CB0/). By using trenches filled with intrinsic silicon adjacent to the collector drift region, the electric field profile can be reshaped so that a high breakdown voltage (>20 V) can be combined with a high drift doping concentration. This allows for high current densities and consequently a high f/sub T/. Experimental results show an increase of the f/sub T//spl times/BV/sub CB0/ product of up to a factor of two by using resurf, the maximum value obtained is 670 GHzV.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126585784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Three-phase sinusoidal current PWM brushless motor driver ICs 三相正弦电流PWM无刷电机驱动集成电路
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239868
T. Yamane, S. Ikeda, A. Nakagawa
{"title":"Three-phase sinusoidal current PWM brushless motor driver ICs","authors":"T. Yamane, S. Ikeda, A. Nakagawa","doi":"10.1109/WCT.2004.239868","DOIUrl":"https://doi.org/10.1109/WCT.2004.239868","url":null,"abstract":"This paper reports a newly developed single packaged IC, integrating a 500 V 1 A one chip inverter IC and its controller chip. The developed ICs greatly reduce the footprints and realize an optimized solution for sinusoidal current PWM drive of DC brushless motors.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126929143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Small-sized motor driver IC 小型电机驱动IC
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239869
N. Fuji
{"title":"Small-sized motor driver IC","authors":"N. Fuji","doi":"10.1109/WCT.2004.239869","DOIUrl":"https://doi.org/10.1109/WCT.2004.239869","url":null,"abstract":"Summary form only given. This paper outlines the use of Hall sensors and PWM control in the design of a driver IC for three-phase full wave control of a DC brushless motor. It describes the 180 degree conduction pseudo-linear wave current drive, V-I conversion and wave composition, current amplification, and 120 degree conduction soft-switching wave current drive, used in this IC.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116913585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Breaking the scaling barrier of large area lateral power devices: an 1m/spl Omega/ flip-chip power MOSFET with ultra low gate charge 突破大面积横向功率器件的标度障碍:超低栅极电荷的1m/spl ω /倒装功率MOSFET
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240220
Z. Shen, D. Okada, F. Lin, A. Tintikakis, S. Anderson
{"title":"Breaking the scaling barrier of large area lateral power devices: an 1m/spl Omega/ flip-chip power MOSFET with ultra low gate charge","authors":"Z. Shen, D. Okada, F. Lin, A. Tintikakis, S. Anderson","doi":"10.1109/WCT.2004.240220","DOIUrl":"https://doi.org/10.1109/WCT.2004.240220","url":null,"abstract":"The conduction performance of low-voltage lateral power semiconductor devices deteriorates considerably with increasing device size due to the parasitic resistance of metal interconnects, commonly known as the \"scaling limitation\". In this paper, we introduce an innovative concept to overcome the problem by integrating a unique metal interconnect scheme with chip-scale packaging. We have designed and fabricated a sub-10 V class power MOSFET with a record-low R/sub DSON/ of 1 m/spl Omega/ at a gate voltage of 6 V, or 1.25 m/spl Omega/ at a gate voltage of 4.5 V, approximately 50% of the lowest R/sub DSON/ previously reported. The new device has a total gate charge Q/sub g/ of 22 nC at 4.5 V and a performance figure of merit of less than 30 m/spl Omega/-nC. This represents a 3/spl times/ improvement over the state of the art trench MOSFETs. The new MOSEFT technology can be used to enable next-generation, multi-MHz, high-density DC/DC converters for future CPU cores and many other high-performance power management applications.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128604061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
New generation metal base free IGBT module structure with low thermal resistance 新一代无金属基IGBT模块结构，低热阻
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240149
Y. Nishimura, E. Mochizuki, M. Kikuchi, T. Nishizawa, Y. Ikeda, Y. Takahashi
{"title":"New generation metal base free IGBT module structure with low thermal resistance","authors":"Y. Nishimura, E. Mochizuki, M. Kikuchi, T. Nishizawa, Y. Ikeda, Y. Takahashi","doi":"10.1109/WCT.2004.240149","DOIUrl":"https://doi.org/10.1109/WCT.2004.240149","url":null,"abstract":"Thermal resistance is one of the most important characteristics in the application of power semiconductors. This paper presents a new generation metal base free IGBT module structure with low thermal resistance. In the experimental results of our new product using the new metal base free structure, heat resistance is reduced by approximately 30% in comparison with the conventional structure. And we achieved improved mechanical strength and reliability characteristics. This was achieved by using a thick copper foil with our original thin zirconia doped alumina technology.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new-generation hybrid electric vehicle and its supporting power semiconductor devices 一种新一代混合动力汽车及其配套功率半导体器件
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240285
A. Kawahashi
{"title":"A new-generation hybrid electric vehicle and its supporting power semiconductor devices","authors":"A. Kawahashi","doi":"10.1109/WCT.2004.240285","DOIUrl":"https://doi.org/10.1109/WCT.2004.240285","url":null,"abstract":"A new-generation Toyota hybrid system called THS II has been developed for a passenger car, the Prius. THS II is based on the \"hybrid synergy drive\" concept. It has achieved high levels of compatibility between environmental performance and power. It has adopted a variable-voltage system in which a boost converter raises the voltage of a battery to higher voltages in a controlled manner. The motor power has increased to 1.5-times higher output. This paper describes the basic operations of THS II, its power electronics systems and components, and its supporting power semiconductor devices.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"44 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129282571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 109
Trench gate power MOSFETs with retrograde body profile 具有逆行体型的沟槽栅极功率mosfet
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239934
B. Tsui, Ming-da Wu, T. Gan, Hui-Hua Chou, Zhi-Liang Wu, C. Sune
{"title":"Trench gate power MOSFETs with retrograde body profile","authors":"B. Tsui, Ming-da Wu, T. Gan, Hui-Hua Chou, Zhi-Liang Wu, C. Sune","doi":"10.1109/WCT.2004.239934","DOIUrl":"https://doi.org/10.1109/WCT.2004.239934","url":null,"abstract":"Low specific on-resistance (R/sub ds,on/) and low gate capacitance are essential for trench gate power MOSFETs. In this work, we propose a simple method of retrograde body profile to improve the two parameters simultaneously. The retrograde body MOSFET (RBMOS) is realized by high energy implantation. Because the highest channel concentration is located close to the drain side, the depletion width at the drain side is suppressed, so that the channel length can be shortened greatly without sacrificing punch-through voltage. A low thermal budget and easy trench gate process are additional benefits. A power MOSFET with channel length of 0.4 /spl mu/m, threshold voltage of 1 V, and breakdown voltage of 32 V is demonstrated. Compared with the conventional device, the specific on-resistance and the figure-of-merit can be improved by 38% and 70%, respectively.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116045711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high efficiency ultra-deep sub-micron DC-DC converter for microprocessor applications 一种用于微处理器应用的高效超深亚微米DC-DC转换器
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239751
B. Reed, K. Ovens, J. Chen, V. Mayega, S. Issa
{"title":"A high efficiency ultra-deep sub-micron DC-DC converter for microprocessor applications","authors":"B. Reed, K. Ovens, J. Chen, V. Mayega, S. Issa","doi":"10.1109/WCT.2004.239751","DOIUrl":"https://doi.org/10.1109/WCT.2004.239751","url":null,"abstract":"An integral part of the voltage scaling system for a microprocessor is the high-efficiency DC-DC converter, which directly provides the core Vdd. Built in an ultra-deep sub-micron (UDSM) baseline 90 nm process, this converter must meet several challenging design constraints. First, using only 30 angstrom CMOS, the design must convert to the nominal core voltage of 1.2 V from a direct-battery input that can be as high as 5.4 V. Second, the converter must detect the output current to switch between pulse-frequency modulation (PFM) and pulse-width modulation (PWM) modes thereby enabling efficient conversion at a broad range of loads. Finally, since there is no post-regulation of the output, this converter must have improved output accuracy without any additional external components. This paper highlights the design techniques used to overcome these challenges as well as the optimizations that can be done when the converter is fully integrated with the microprocessor. Also discussed are future designs that will migrate this converter to the baseline 65 nm process.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115423986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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