Mixed mode 3D pseudo-1chip ESD surge simulation using hydrodynamic model for new LDMOS cell layout realizing super high ESD endurance over 25kV/mm2

Abstract

For the first time, a new ESD surge simulation method that combines a 3D pseudo-1chip device model, consisting of an internal LDMOS cell and peripheral LDMOS cell, and a hydrodynamic physical model, is proposed in order to analyze the ESD destruction mechanism of LDMOS and optimize the cell layout against ESD. The simulation results show good agreement with experiments on ESD endurance and surge current crowding phenomena at the peripheral cell, causing poor ESD endurance. Utilizing the proposed simulation method, we developed a new LDMOS cell layout, achieving super high ESD endurance over 25 kV/mm/sup 2/.