A high efficiency ultra-deep sub-micron DC-DC converter for microprocessor applications

Abstract

An integral part of the voltage scaling system for a microprocessor is the high-efficiency DC-DC converter, which directly provides the core Vdd. Built in an ultra-deep sub-micron (UDSM) baseline 90 nm process, this converter must meet several challenging design constraints. First, using only 30 angstrom CMOS, the design must convert to the nominal core voltage of 1.2 V from a direct-battery input that can be as high as 5.4 V. Second, the converter must detect the output current to switch between pulse-frequency modulation (PFM) and pulse-width modulation (PWM) modes thereby enabling efficient conversion at a broad range of loads. Finally, since there is no post-regulation of the output, this converter must have improved output accuracy without any additional external components. This paper highlights the design techniques used to overcome these challenges as well as the optimizations that can be done when the converter is fully integrated with the microprocessor. Also discussed are future designs that will migrate this converter to the baseline 65 nm process.