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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs最新文献

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IEGT design criterion for reducing EMI noise [injection enhancement gate transistor] 降低电磁干扰噪声的IEGT设计准则[注入增强栅极晶体管]
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239838
M. Yamaguchi, I. Omura, S. Urano, S. Umekawa, M. Tanaka, T. Okuno, T. Tsunoda, T. Ogura
{"title":"IEGT design criterion for reducing EMI noise [injection enhancement gate transistor]","authors":"M. Yamaguchi, I. Omura, S. Urano, S. Umekawa, M. Tanaka, T. Okuno, T. Tsunoda, T. Ogura","doi":"10.1109/WCT.2004.239838","DOIUrl":"https://doi.org/10.1109/WCT.2004.239838","url":null,"abstract":"The EMI noise of an IGBT/IEGT (injection enhancement gate transistor) circuit is significantly reduced by introducing a new device design criterion. The design criterion improves dV/sub CE//dt controllability during the IEGT turn-on transient without sacrificing the featured low saturation voltage of the IEGT structure. The perfectly floating p-well region, as the criterion, prevents the undesirable V/sub GE/ overshoot and the resultant uncontrollable dV/sub CE//dt. The design criterion has been applied to a 1200 V ultra thin PT-IEGT, and low noise turn-on characteristics have been experimentally obtained. IEGTs with the new criterion enable low noise operation and precise gate control, which are suitable for active gate drive.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125337763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Digital input audio power amplifiers in 0.6-/spl mu/m BCD technology: two examples 数字输入音频功率放大器在0.6-/spl mu/m BCD技术:两个例子
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239811
E. Botti, A. Grosso, C. Meroni, F. Stefani
{"title":"Digital input audio power amplifiers in 0.6-/spl mu/m BCD technology: two examples","authors":"E. Botti, A. Grosso, C. Meroni, F. Stefani","doi":"10.1109/WCT.2004.239811","DOIUrl":"https://doi.org/10.1109/WCT.2004.239811","url":null,"abstract":"In consumer electronics, the digital processing of the audio signal is becoming preferred with respect to the \"old\" analog processing. The last block still with analog input and full analog processing is the audio power amplifier. Thanks to the high-density BCD technology it is now possible to implement a low-cost single-chip audio power amplifier with digital input. In this paper two examples are presented, exploring respectively the switching technique (PWM) and the linear class-AB output stage.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127300937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SoC integration challenges for a power management/analog baseband IC for 3G wireless chipsets 用于3G无线芯片组的电源管理/模拟基带IC的SoC集成挑战
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239807
D. Evans, M. McConnell, P. Kawamura, L. Krug
{"title":"SoC integration challenges for a power management/analog baseband IC for 3G wireless chipsets","authors":"D. Evans, M. McConnell, P. Kawamura, L. Krug","doi":"10.1109/WCT.2004.239807","DOIUrl":"https://doi.org/10.1109/WCT.2004.239807","url":null,"abstract":"An integrated power management/analog baseband integrated circuit has been developed in 0.35 /spl mu/m CMOS technology. The IC features multiple low-dropout (LDO) linear voltage regulators, power switches, DC/DC switching converters, a voice band CODEC, and WCDMA and GSM baseband converters all sharing the same substrate. This paper examines the design challenges associated with power management and analog baseband system on a chip (SoC) integration. Optimal floorplanning, power device isolation, shielding, power distribution, reference generation, and noise reduction strategies and techniques are discussed.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121554683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
550 V superjunction 3.9 /spl Omega/mm/sup 2/ transistor formed by 25 MeV masked boron implantation 550v超结3.9 /spl ω /mm/sup 2/晶体管由25mev掩膜硼注入形成
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239754
M. Rub, M. Bar, G. Deboy, F.-J. Niedemostheide, M. Schmitt, H. Schulze, A. Willmeroth
{"title":"550 V superjunction 3.9 /spl Omega/mm/sup 2/ transistor formed by 25 MeV masked boron implantation","authors":"M. Rub, M. Bar, G. Deboy, F.-J. Niedemostheide, M. Schmitt, H. Schulze, A. Willmeroth","doi":"10.1109/WCT.2004.239754","DOIUrl":"https://doi.org/10.1109/WCT.2004.239754","url":null,"abstract":"For the first time, we present experimental work on superjunction devices, in which the deep p-columns have been formed by a multi-step high-energy implantation. The desired blocking voltage and the Ron /spl times/ A are in the range of 500 V-600 V and about 3.5 - 4.0 /spl Omega/mm/sup 2/, respectively. Deep (32 /spl mu/m) p-n junctions were formed by using a set of five boron implantation energies ranging from 3 to 25 MeV. Masking was achieved by silicon stencil masks which were glued to the device wafers.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121721914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Trench power MOSFET lowside switch with optimized integrated Schottky diode 沟槽功率MOSFET低侧开关，优化集成肖特基二极管
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240290
D. Calafut
{"title":"Trench power MOSFET lowside switch with optimized integrated Schottky diode","authors":"D. Calafut","doi":"10.1109/WCT.2004.240290","DOIUrl":"https://doi.org/10.1109/WCT.2004.240290","url":null,"abstract":"This work investigates the device and circuit performance of an integrated MOSFET-Schottky diode solution for lowside switching, or synchronous rectifier, applications. The integrated diode structure is a trench MOS barrier Schottky (TMBS) device, and the area of the TMBS structure, as a ratio of the total active area, was the independent variable in this study, ranging from zero to 50%. The results of both simulation and experiments show that there is an optimum contribution of TMBS area which maximizes the performance of the integrated device. Initially, the results provided a strong correlation between TMBS contribution, diode recovery characteristics, and DC-DC converter efficiency. However, a closer examination of the underlying, device level current distribution waveforms, as well as the power loss mechanisms in the converter, reveal a more complex interaction of the TMBS structure and the MOSFET. It is only in the context of this analysis, that useful device design insight can be extracted.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125021724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Novel high power semiconductor module for trench IGBTs 用于沟槽igbt的新型高功率半导体模块
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240148
T. Stockmeier, Y. Manz, J. Steger
{"title":"Novel high power semiconductor module for trench IGBTs","authors":"T. Stockmeier, Y. Manz, J. Steger","doi":"10.1109/WCT.2004.240148","DOIUrl":"https://doi.org/10.1109/WCT.2004.240148","url":null,"abstract":"A new high power IGBT module is presented here, which is particularly suited for devices with low forward voltage drop, such as the latest trench IGBTs. The module design is versatile to cover a power range from 190 A to 1000 A, to enable integrated drive and protection functions, and to address different circuit topologies. Its unique construction features are spring pins to the gate and emitter of each individual IGBT chip, the elimination of wire bonding to power terminals, and scalable subunits. This results in lower losses, better cooling, and optimized parallelling of chips and modules.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131375346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design and fabrication of SiC MESFET transistor and broadband power amplifier for RF applications 用于射频应用的SiC MESFET晶体管和宽带功率放大器的设计与制造
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240036
P. Chen, H. R. Chang, X. Li, B. Luo
{"title":"Design and fabrication of SiC MESFET transistor and broadband power amplifier for RF applications","authors":"P. Chen, H. R. Chang, X. Li, B. Luo","doi":"10.1109/WCT.2004.240036","DOIUrl":"https://doi.org/10.1109/WCT.2004.240036","url":null,"abstract":"A SiC MESFET package and a prototype power amplifier module were demonstrated with P/sub 1dB/ output power of 26 W and 35 W, respectively. High power and high power gain were maintained through 950 MHz to 1500 MHz L-band operation across 500 MHz bandwidth for the SiC PA module, which is a critical challenge to other semiconductor devices.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131602647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An ultra-low R/sub ons/ in 4H-SiC vertical MOSFET: buried channel double-epitaxial MOSFET 超低R/sub - ons/ in 4H-SiC垂直MOSFET:埋沟道双外延MOSFET
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.240035
S. Harada, M. Okamoto, T. Yatsuo, K. Adachi, K. Fukuda, K. Arai
{"title":"An ultra-low R/sub ons/ in 4H-SiC vertical MOSFET: buried channel double-epitaxial MOSFET","authors":"S. Harada, M. Okamoto, T. Yatsuo, K. Adachi, K. Fukuda, K. Arai","doi":"10.1109/WCT.2004.240035","DOIUrl":"https://doi.org/10.1109/WCT.2004.240035","url":null,"abstract":"This study developed a novel 4H-SiC vertical MOSFET device structure, named double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup -/ epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega/cm/sup 2/ at a gate voltage of 15 V when the blocking voltage is 600 V. The simulation results revealed that the characteristics largely depend on the profile of the nitrogen in the n-type region between the p-wells.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124672902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Influence of temperature and doping parameters on the performance of segmented anode NPN (SA-NPN) LIGBT 温度和掺杂参数对分段阳极NPN (SA-NPN) light性能的影响
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239989
D. Green, S. Hardikar, M. Sweet, K. Vershinin, R. Tadikonda, M. M. De Souza, E. Narayanan
{"title":"Influence of temperature and doping parameters on the performance of segmented anode NPN (SA-NPN) LIGBT","authors":"D. Green, S. Hardikar, M. Sweet, K. Vershinin, R. Tadikonda, M. M. De Souza, E. Narayanan","doi":"10.1109/WCT.2004.239989","DOIUrl":"https://doi.org/10.1109/WCT.2004.239989","url":null,"abstract":"An ultra-high performance SA-NPN anode LIGBT is presented. In contrast to other structures, the SA-NPN offers controllability of the device characteristics at the design stage through a simple variation in the ratio of NPN/P+ widths. The performance advantages of the SA-NPN LIGBT in comparison to a conventional structure at both room and elevated temperatures clearly demonstrate that the SA-NPN is one of the best in the class of anode engineering for lateral power devices.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130828563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Peripheral motor drive PIC concerns for integrated LDMOS technologies 外围电机驱动PIC集成LDMOS技术的关注
2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI: 10.1109/WCT.2004.239871
B. Smith, J. Xu, J. Devore, A. Chellamuthu, B. Amey, S. Pendharkar, T. Efland
{"title":"Peripheral motor drive PIC concerns for integrated LDMOS technologies","authors":"B. Smith, J. Xu, J. Devore, A. Chellamuthu, B. Amey, S. Pendharkar, T. Efland","doi":"10.1109/WCT.2004.239871","DOIUrl":"https://doi.org/10.1109/WCT.2004.239871","url":null,"abstract":"This work reviews common motor types, driving methods, and associated requirements of power LDMOS drivers including BVdss, Rdson, and SOA for peripheral product applications up to 60 V. Tradeoffs made between various processes, power efficiency, and circuit implementations are discussed. The paper explores additional motor driving specific concerns such as substrate injection, parasitic npn/pnp effects and robustness, reverse recovery, and ESD. Up integration concerns and sensitive circuit isolation techniques are also included. The introduction includes a short process technology outline for peripheral product power ICs (PICs).","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114200191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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