SoC integration challenges for a power management/analog baseband IC for 3G wireless chipsets

Abstract

An integrated power management/analog baseband integrated circuit has been developed in 0.35 /spl mu/m CMOS technology. The IC features multiple low-dropout (LDO) linear voltage regulators, power switches, DC/DC switching converters, a voice band CODEC, and WCDMA and GSM baseband converters all sharing the same substrate. This paper examines the design challenges associated with power management and analog baseband system on a chip (SoC) integration. Optimal floorplanning, power device isolation, shielding, power distribution, reference generation, and noise reduction strategies and techniques are discussed.