M. Yamaguchi, I. Omura, S. Urano, S. Umekawa, M. Tanaka, T. Okuno, T. Tsunoda, T. Ogura
{"title":"IEGT design criterion for reducing EMI noise [injection enhancement gate transistor]","authors":"M. Yamaguchi, I. Omura, S. Urano, S. Umekawa, M. Tanaka, T. Okuno, T. Tsunoda, T. Ogura","doi":"10.1109/WCT.2004.239838","DOIUrl":null,"url":null,"abstract":"The EMI noise of an IGBT/IEGT (injection enhancement gate transistor) circuit is significantly reduced by introducing a new device design criterion. The design criterion improves dV/sub CE//dt controllability during the IEGT turn-on transient without sacrificing the featured low saturation voltage of the IEGT structure. The perfectly floating p-well region, as the criterion, prevents the undesirable V/sub GE/ overshoot and the resultant uncontrollable dV/sub CE//dt. The design criterion has been applied to a 1200 V ultra thin PT-IEGT, and low noise turn-on characteristics have been experimentally obtained. IEGTs with the new criterion enable low noise operation and precise gate control, which are suitable for active gate drive.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WCT.2004.239838","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
The EMI noise of an IGBT/IEGT (injection enhancement gate transistor) circuit is significantly reduced by introducing a new device design criterion. The design criterion improves dV/sub CE//dt controllability during the IEGT turn-on transient without sacrificing the featured low saturation voltage of the IEGT structure. The perfectly floating p-well region, as the criterion, prevents the undesirable V/sub GE/ overshoot and the resultant uncontrollable dV/sub CE//dt. The design criterion has been applied to a 1200 V ultra thin PT-IEGT, and low noise turn-on characteristics have been experimentally obtained. IEGTs with the new criterion enable low noise operation and precise gate control, which are suitable for active gate drive.