集成垂直DMOS晶体管ESD稳健性优化

2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI:10.1109/WCT.2004.239936

P. Moens, K. Reynders, S. Bychikhin, D. Pogany, M. Zubeidat

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引用次数: 5

摘要

本文分析了垂直集成DMOS晶体管的ESD稳健性。建立了回跳电流(I/sub sb/)与器件布局、热失效电流(I/sub tf/)与埋地层工艺条件之间的关系。导致热点在两个相邻的垂直双极之间跳跃的物理机制;突出显示。ESD稳健性的优化意味着放弃R/sub /。确定了最佳工艺和布置条件。

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Optimization of integrated vertical DMOS transistors for ESD robustness

This paper analyses the ESD robustness of vertically integrated DMOS transistors. The relation between the snapback current (I/sub sb/) and the device layout, and between the thermal failure current (I/sub tf/) and the buried layer process conditions is established. The physical mechanisms responsible for hot spot hopping between two adjacent vertical bipolars; are highlighted. Optimisation for ESD robustness means giving up on R/sub on/. The optimum process and layout conditions are determined.

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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs

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