{"title":"30V sub-micron shallow junction planar-MOSFET for DC-DC converters","authors":"S. Ono, Y. Yamaguchi, Y. Kawaguchi, A. Nakagawa","doi":"10.1109/WCT.2004.240291","DOIUrl":null,"url":null,"abstract":"We present sub-micron shallow p-base planar-DMOSFETs (DMOS: double diffused MOSFET type) for DC-DC converter applications. The shallow junction depth is quite useful to reduce the device on-resistance. It was found that the gate-drain feedback charge can effectively be reduced by adopting a very narrow and shallow JFET region with very high JFET donor concentration, based on the charge compensation theory. An experimental planar DMOSFET with p-base depth of 0.8 /spl mu/m exhibited a breakdown voltage of 34 V, an Ron*Qgd of 14.9 m/spl Omega/nC, and good UIS capability. This is the best value ever reported for a 30 V planar DMOSFET structure.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"94 10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WCT.2004.240291","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
We present sub-micron shallow p-base planar-DMOSFETs (DMOS: double diffused MOSFET type) for DC-DC converter applications. The shallow junction depth is quite useful to reduce the device on-resistance. It was found that the gate-drain feedback charge can effectively be reduced by adopting a very narrow and shallow JFET region with very high JFET donor concentration, based on the charge compensation theory. An experimental planar DMOSFET with p-base depth of 0.8 /spl mu/m exhibited a breakdown voltage of 34 V, an Ron*Qgd of 14.9 m/spl Omega/nC, and good UIS capability. This is the best value ever reported for a 30 V planar DMOSFET structure.