用于DC-DC变换器的30V亚微米浅结平面mosfet

2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI:10.1109/WCT.2004.240291

S. Ono, Y. Yamaguchi, Y. Kawaguchi, A. Nakagawa

{"title":"用于DC-DC变换器的30V亚微米浅结平面mosfet","authors":"S. Ono, Y. Yamaguchi, Y. Kawaguchi, A. Nakagawa","doi":"10.1109/WCT.2004.240291","DOIUrl":null,"url":null,"abstract":"We present sub-micron shallow p-base planar-DMOSFETs (DMOS: double diffused MOSFET type) for DC-DC converter applications. The shallow junction depth is quite useful to reduce the device on-resistance. It was found that the gate-drain feedback charge can effectively be reduced by adopting a very narrow and shallow JFET region with very high JFET donor concentration, based on the charge compensation theory. An experimental planar DMOSFET with p-base depth of 0.8 /spl mu/m exhibited a breakdown voltage of 34 V, an Ron*Qgd of 14.9 m/spl Omega/nC, and good UIS capability. This is the best value ever reported for a 30 V planar DMOSFET structure.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"94 10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"30V sub-micron shallow junction planar-MOSFET for DC-DC converters\",\"authors\":\"S. Ono, Y. Yamaguchi, Y. Kawaguchi, A. Nakagawa\",\"doi\":\"10.1109/WCT.2004.240291\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present sub-micron shallow p-base planar-DMOSFETs (DMOS: double diffused MOSFET type) for DC-DC converter applications. The shallow junction depth is quite useful to reduce the device on-resistance. It was found that the gate-drain feedback charge can effectively be reduced by adopting a very narrow and shallow JFET region with very high JFET donor concentration, based on the charge compensation theory. An experimental planar DMOSFET with p-base depth of 0.8 /spl mu/m exhibited a breakdown voltage of 34 V, an Ron*Qgd of 14.9 m/spl Omega/nC, and good UIS capability. This is the best value ever reported for a 30 V planar DMOSFET structure.\",\"PeriodicalId\":303825,\"journal\":{\"name\":\"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs\",\"volume\":\"94 10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WCT.2004.240291\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WCT.2004.240291","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 13

摘要

我们提出亚微米浅p基平面dmosfet (DMOS:双扩散MOSFET类型)用于DC-DC转换器应用。浅结深度对减小器件导通电阻非常有用。基于电荷补偿理论，采用极窄且极浅的JFET供体浓度可以有效地降低栅极-漏极反馈电荷。实验得到p基深度为0.8 /spl mu/m的平面DMOSFET击穿电压为34 V, Ron*Qgd为14.9 m/spl ω /nC，具有良好的UIS性能。这是迄今为止报道的30 V平面DMOSFET结构的最佳值。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

30V sub-micron shallow junction planar-MOSFET for DC-DC converters

We present sub-micron shallow p-base planar-DMOSFETs (DMOS: double diffused MOSFET type) for DC-DC converter applications. The shallow junction depth is quite useful to reduce the device on-resistance. It was found that the gate-drain feedback charge can effectively be reduced by adopting a very narrow and shallow JFET region with very high JFET donor concentration, based on the charge compensation theory. An experimental planar DMOSFET with p-base depth of 0.8 /spl mu/m exhibited a breakdown voltage of 34 V, an Ron*Qgd of 14.9 m/spl Omega/nC, and good UIS capability. This is the best value ever reported for a 30 V planar DMOSFET structure.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs

自引率

0.00%

发文量