Drain voltage dependence of on resistance in 700V super junction LDMOS transistor

In this paper, the dependence of the specific on resistance R/sub DS/*A on drain voltage V/sub D/ is presented for the first time for 700 V super junction (SJ) based multi-RESURF LDMOS transistors and such results are compared to those of single-RESURF (SR) and double-RESURF (DR) LDMOS transistors. Based on ISE based 3D device simulation results, it has been demonstrated that even the decrease in the width of the NP stripes of the SJ structure results in significant improvement in R/sub DS/*A. Such improvement suffers greatly at high drain bias V/sub D/ due to an increased influence in the constriction of the current conduction path due to the large depletion effect.