2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献_第4页

Twin-GD: A New Twin Gated-Diode Measurement for the Interface Characterization of Ultra-Thin Gate Oxide MOSFET's with EOT Down to 1nm Twin- gd:一种新的双门二极管测量方法，用于EOT低至1nm的超薄栅氧化MOSFET的界面表征

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.250992

G.D. Lee, S.S. Chung, A. Mao, W. Lin, C.W. Yang, Y. S. Hsieh, K. Chu, L. W. Cheng, H. Tai, L. T. Hsu, C.R. Lee, H. Meng, C. Tsai, G. H. Ma, S. Chien, S. Sun

引用次数: 0

Characterization of a Burn-in Failure Caused by a Defective Source Driver on TFT-LCD Panel TFT-LCD面板上由缺陷源驱动引起的老化故障的表征

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251023

F.‐S. Wang, Keh-La Lin, K. Tso, Chin-Chieh Chao, W.W. Wang, Alan Yu, C.Y. Lee, Chien Hung Kuo, C.W.A. Wang, Yi Chiu

引用次数: 0

A Study of Center Field Stripe Yield Loss Mechanism 中心场条纹产量损失机理研究

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251025

A. Maurya, M.J. Bin Manaf, Z. Abdul Rahman, Sim Jit-Shen, Cheng Soon Ong, Thung Beng Joo

{"title":"A Study of Center Field Stripe Yield Loss Mechanism","authors":"A. Maurya, M.J. Bin Manaf, Z. Abdul Rahman, Sim Jit-Shen, Cheng Soon Ong, Thung Beng Joo","doi":"10.1109/IPFA.2006.251025","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251025","url":null,"abstract":"Detection of killer defects is critical to improving yields in VLSI fabrication. Bright and dark-field inspection tools detect both killer and non-killer defects, and in some cases a high level of nuisance defects may adversely affect the ability to monitor and eliminate the real ones that have a detrimental impact on device yield. E-beam inspection tools take advantage of a phenomenon referred to as voltage contrast, and can differentiate between grounded and floating structures, thus detecting electrical killer defects. A particularly useful application of e-beam inspection is the detection of highly resistive or not-fully opened vias. Finding these types of failures with standard bright or dark-field inspection tools is extremely difficult, given the high aspect ratio and small width of typical vias. Figures showed the basic principle of e-beam analysis for vias. The sample is subjected to the analysis after via etch and barrier deposition. Vias that are fully open have good electrical connection to ground, and appear dark. Vias that are not properly open because of for example, residual dielectric material at the bottom, are electrically floating, and appear bright. This paper reports on a problem with one of the Silterra devices that suffered from sporadic cases of yield loss affecting dies on the center column of the 3times3 reticle field. Vertical stripes of failed dies would thus appear on the wafer sort maps. The failure bin (Bin 60) indicated a problem with the SRAM portion of the device. Based on the suspicion of a Vial problem, e-beam analysis was used to investigate via integrity. The motivation of this work was to find the root cause of the problem and implement a permanent solution","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132564253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Localization of Electrical Shorts in Dies and Packages using Magnetic Microscopy and Lock-in-IR Thermography 利用磁显微镜和锁定红外热成像技术定位模具和封装中的电短路

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251041

M. Hechtl, G. Steckert, C. Keller

引用次数: 11

A Spectroscopic SEM: First Results A光谱扫描电镜:初步结果

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.250996

M. Osterberg, A. Khursheed

引用次数: 0

Thermal Reliability of Cu/low -κ(Black-DiamondTM, BD) Interconnects on Flexible Organic Substrate 柔性有机衬底上Cu/low -κ(Black-DiamondTM, BD)互连的热可靠性

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251010

H.Y. Li, J. Bai, H. Chua, L.H. Guo, G. Lo

引用次数: 0

Understanding Protective Overcoat Damages: Failure Analysis to the Next Level 了解保护层损坏:失效分析到下一个层次

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251024

F.V. Abitan, R. C. Angeles, M. Fabia, R. Flores, C.B. Gabunas

{"title":"Understanding Protective Overcoat Damages: Failure Analysis to the Next Level","authors":"F.V. Abitan, R. C. Angeles, M. Fabia, R. Flores, C.B. Gabunas","doi":"10.1109/IPFA.2006.251024","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251024","url":null,"abstract":"Failure analysis (FA) is key in root cause identification for any problem solving journey. Diagnosis given provides insights on mechanisms by which failures occur. This helps in determining factors that lead to the failure and consequently the root cause, thus easier to provide corrective actions. In mid June 2004, a sudden increase in test fall-outs was encountered. Several devices from different product groups were affected. Fail modes reported were supply shorts and functional fails. FA on rejects showed PO damages with burnt metals as the physical defect of the rejects. PO damages are commonly induced mechanically. Burnt metals, on the other hand, are usually identified with electrical overstress (EOS) or electro-static discharge (ESD) related event. Both features were observed on inspected rejects; hence root-cause identification became a challenge. Conflicting views from counterparts added to the confusion. Experts in the US leaned on the EOS or ESD side of the case while counterparts in France maintained the mechanical angle of the issue. These conflicting inputs brought about different insights on different mechanisms leading to PO damages","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Hot-Carrier Reliability of NLDEMOS in 0.13μm SOI CMOS Technology NLDEMOS在0.13μm SOI CMOS技术中的热载流子可靠性

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251002

D. Lachenal, Y. Rey-Tauriac, L. Boissonnet, B. Reynard, A. Bravaix

引用次数: 2

Fabrication of high Ge content SiGe layer on Si by Ge condensation technique 用锗缩合技术在硅表面制备高锗含量的SiGe层

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251050

S. Balakumar, T. Jun wei, C. Tung, G. Lo, H. Nguyen, C. Fong, A. Agarwal, R. Kumar, N. Balasubramanian, S.J. Lee, D. Kwong

引用次数: 3

Abnormal ESD Damages Occur in Interface Circuits between Different Power Domains in ND-Mode MM ESD Stress 在nd模MM的ESD应力中，不同功率域之间的接口电路会出现异常的ESD损伤

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251021

Hsiang-Pin Hung, M. Ker, Shih-Hung Chen, Che-Hao Chuang

引用次数: 5