{"title":"TEM application in the failure analysis of advanced 90 nm SOI-based IC devices","authors":"K. Li, E. Er, S. Zhao","doi":"10.1109/IPFA.2006.251031","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251031","url":null,"abstract":"The adoption of SOI structure into 90 nm IC devices makes the characterization very challenging. TEM characterization becomes more critical, challenging and indispensable in the failure analysis of such devices. To illustrate the application of TEM in this area, several unique examples including both cross-sectional and planar analysis are given here","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131111136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dong-Sun Kim, Wonjoon Ho, Jae-Yeong Kim, Eui-Yong Shin, Jin-ha Kim, H. Lee
{"title":"New Failure Analysis of Tungsten Plug Corrosion in Via Process","authors":"Dong-Sun Kim, Wonjoon Ho, Jae-Yeong Kim, Eui-Yong Shin, Jin-ha Kim, H. Lee","doi":"10.1109/IPFA.2006.250986","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250986","url":null,"abstract":"In this paper, systematic pair bit failure is analyzed in failure bit map of deep-submicron CMOS technology. Tungsten plug corrosion in contacts of stacked contact/metal/via structure is observed from careful analysis of failure bit. Then, some experiments have been carried out to identify and resolve this corrosion failure. This corrosion reaction occurred through the void space, which is formed by excess via over-etch along the sidewall of underlying metal in contact-metal-via stack structure and by the plasma charging and electrochemical reaction during via etch and post cleaning. This failure can be practically avoided by optimizing via over-etch time and underlying metal profile and it is confirmed by product yield and failure bit map data","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128378654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study on Potassium Contamination in SOI Wafer Fabrication Using Dynamic SIMS","authors":"D. Gui, Y. Hua, X.Z. Xing, S.P. Zhao","doi":"10.1109/IPFA.2006.251014","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251014","url":null,"abstract":"In this paper, a case study of BIST failure in SOI wafer fabrication was presented. With optimized charge neutralization using a well-controlled normal incident electron beam, a reliable depth distribution of K in the ILD was obtained which is helpful to understand the source of K contamination. From the SIMS and EDX results, the root cause was concluded to be K contamination introduced by the CMP slurry. The yield has been improved greatly by depositing a layer of high density oxide on the top of ILD to block the K contamination","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131644132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Frémont, M. Mura, B. Piano, W. Horaud, Y. Dantov
{"title":"Impact of the PCB design on the crack risk of CSP assemblies subjected to temperature cycling and drop tests","authors":"H. Frémont, M. Mura, B. Piano, W. Horaud, Y. Dantov","doi":"10.1109/IPFA.2006.251036","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251036","url":null,"abstract":"Especially in the handheld context, we need always greater guarantees in product efficiency. Mobiles, notebooks, organizers, cameras etc. are assets whose use increases the probability of downfall. When an electronic product drops on the ground, impact force and deformation is transferred internally to the printed circuit board (PCB), solder joints and the integrated circuits (IC) packages. The IC packages are susceptible to solder joint cracks, induced by a combination of PCB bending and mechanical shock during the impact event. If a single drop event does not cause failure, repeated drop events can cause impact fatigue or accumulated damage and rupture of interconnection joints and assembly materials. Drop testing provides a useful experimental approach to design for drop reliability. Numerous are the studies on micro-assembly welding reliability, in which soldering, and also of a series of factors closely correlate such as the pad designs, finishes effects, choice of the materials, process techniques are taken into account. At the same time a European directive (RoHS) on the restriction of the dangerous substances, establishes the exclusion of lead from the electrical and electronic devices except for same applications. As a result, the Sn-Pb solders, commonly used in microelectronics chip packages, should be replaced by lead-free solder with a comparable, or preferably better, reliability. Sn-Ag-Cu eutectic seems to be one of the best candidates. In this study, the impact of PCB design on the failure risk of CSPs assemblies after temperature cycling and drop test was investigated. Different pad geometries, added to the most prevalent protective finishes were tested on Pb-based as well as on lead-free solder pastes. This paper aims to determinate the relationships between process effects, like voids or solder joints deformation and failures, but up to now only based on comparisons","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123743881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Gao, S. Balakumar, Li Rui, S.J. Lee, C. Tung, A. Du, T. Sudhiranjan, D. Kwong, W. Hwang, N. Balasubramanian, P. Lo, Chi Dong-zhi
{"title":"100 nm Gate Length Pt-Germanosilicide Schottky S/D PMOSFET on SGOI substrate fabricated by novel condensation approach","authors":"F. Gao, S. Balakumar, Li Rui, S.J. Lee, C. Tung, A. Du, T. Sudhiranjan, D. Kwong, W. Hwang, N. Balasubramanian, P. Lo, Chi Dong-zhi","doi":"10.1109/IPFA.2006.251052","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251052","url":null,"abstract":"Single-crystalline SGOI substrate is achieved by multi-step oxidation of co-sputtered amorphous SiGe film on SOI substrate. Subsequently, SGOI PMOSFET using Pt-germanosilicide Schottky S/D and HfO 2/TaN gate stack integrated with conventional self-aligned top gate process was demonstrated. Excellent performance of the SGOI PMOSFET is presented","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126220975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation of Texture Development Caused Stress Build-Up in Electroplated Copper Lines","authors":"H. Ceric, C. Hollauer, S. Selberherr","doi":"10.1109/IPFA.2006.250987","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250987","url":null,"abstract":"We presented a simulation concept which connects microstructural mechanical properties of copper films to the overall stress distribution. The underlying model is designed by combining several earlier models which describe different microstructural contributions to stress build up. The mechanical effects of surrounding layers are also included in our analysis. The analysis of the models and simulation results and their comparison to the relevant experimental results has been carried out. The simulated stress distribution is comparable to the stresses measured after the deposition of copper films. The basic features of texture evolution seen in simulations are the same as those observed during measurements","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123987771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Advanced Test Methodology and Strategies for Semiconductors","authors":"B. West","doi":"10.1109/IPFA.2006.251011","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251011","url":null,"abstract":"The seemingly relentless progress of Moore's law recently transformed the basic nature of semiconductor test. Today the focus on the high-end devices is evolving from precise measurement to data management. A transaction-based ATE architecture is therefore described","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123709999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The rules of the Rue Morgue: a decade later","authors":"G. Mura, M. Vanzi, G. Cassanelli, F. Fantini","doi":"10.1109/IPFA.2006.251000","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251000","url":null,"abstract":"The paper could limit itself to repeat the complaint that originated the first \"Rules of the Rue Morgue\", maybe updating the scenario of the many end users currently exposed to the risk of failed failure analyses. Nevertheless, some constructive proposals will be also pointed out, as those exposed by a recent paper (Cassanelli et al., 2005) that, dealing with the challenges in system reliability predictions, proposed some shortcuts to include even few field data into that process, and to include F.A. findings, when reliable, to skip cumbersome (and often not available) extraction of reliability parameters by statistical data. More specifically, in both the reported B and C cases the sudden occurrence of the failure mode was not related to any sudden firing of the root failure mechanisms, but other hidden roots have been identified, with completely different corrective actions with respect to the first interpretations. There is a simple and \"correct\" conclusion to this result: by means of thorough analyses, the first specimen (IGBT) was indicted for some higher sensitivity to latch-up, and the second (CMOS) to external EMI-induced ESD events. This could move to correct the corresponding pi factors employed for calculating the actual failure rate lambda drawing a physically sound shortcut to the estimation of the reliability parameters for some critical devices of a given electronic system","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130060188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design for Reliability","authors":"T. Turner","doi":"10.1109/IPFA.2006.251042","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251042","url":null,"abstract":"The ITRS lists several areas where reliability technology needs development. This includes test methods for new materials and processes. However, perhaps the greatest change in reliability assurance is the requirement to place more of the responsibility for reliability assurance into the hands of circuit designers. This stems from the general compromising of reliability to obtain higher performance. Semiconductor processes can no longer be though of as reliable for all designs that pass a few simple design rules. Reliable designs can now only be produced with a significant investment in reliability simulations, cell library testing and advanced test structure development. Designers must look at effects due to parametric distributions, thermal limits, stresses introduced by packages and neutron and alpha particle radiation. The shift of this responsibility to circuit designers will change the traditional foundry/fabless relationship and will likely increase the demands for detailed failure analysis in the future","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125703826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel Sample Preparation Methodology on TIM Materials for TEM Microstructure Study","authors":"C. Chan, X. Zhao, J. Chin","doi":"10.1109/IPFA.2006.251029","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251029","url":null,"abstract":"This paper presents a successful methodology for TEM sample preparation on indium pre-form thermal interface material (TIM), which is currently used in high-performance microprocessor product. Experimental results show that FIB related artifacts are greatly reduced, thus enables phase morphology study of inter-metallic compound (IMC) layers between TIM and IC chip","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122333188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}