New Failure Analysis of Tungsten Plug Corrosion in Via Process

Abstract

In this paper, systematic pair bit failure is analyzed in failure bit map of deep-submicron CMOS technology. Tungsten plug corrosion in contacts of stacked contact/metal/via structure is observed from careful analysis of failure bit. Then, some experiments have been carried out to identify and resolve this corrosion failure. This corrosion reaction occurred through the void space, which is formed by excess via over-etch along the sidewall of underlying metal in contact-metal-via stack structure and by the plasma charging and electrochemical reaction during via etch and post cleaning. This failure can be practically avoided by optimizing via over-etch time and underlying metal profile and it is confirmed by product yield and failure bit map data