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2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

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Apply Difference Analysis to Nano-Probing Technique for Reasoning Erratic Defect out in Integrated Circuits 差分分析在纳米探测技术中对集成电路不稳定缺陷进行推理的应用
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.250984
G. Shen, K. Chuang
{"title":"Apply Difference Analysis to Nano-Probing Technique for Reasoning Erratic Defect out in Integrated Circuits","authors":"G. Shen, K. Chuang","doi":"10.1109/IPFA.2006.250984","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250984","url":null,"abstract":"The purpose of this paper is to present a novel deductive methodology, which is accomplished by applying difference analysis to nano-probing technique. This methodology would like to resolve the erratic device with a tailing failure or puzzling feature, but not only to check if the suspect had incorrect characteristic or mismatched transistor parameters","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117057928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation Study of Hot-electron Reliability in strained-Si n-MOSFETs 应变si - n- mosfet热电子可靠性模拟研究
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251016
C. Maiti, S. Mahato, A. Saha
{"title":"Simulation Study of Hot-electron Reliability in strained-Si n-MOSFETs","authors":"C. Maiti, S. Mahato, A. Saha","doi":"10.1109/IPFA.2006.251016","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251016","url":null,"abstract":"In this paper, we demonstrate for the first time via technology computer aided design (TCAD), the enhancement in both the ac and dc performances for process-induced strained-Si MOSFETs over bulk-Si and a comparison of process-induced strained and substrate-induced strained-Si MOSFETs. In addition, we present the hot-electron degradation characteristics for strained-Si n-MOSFETs fabricated in both the substrate strain (SS) and process-induced strain (PSS) process flows via TCAD. Effects of both the SS and PSS stress on high vertical electric field mobility and threshold voltage shift in n-MOSFETs are also reported","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127127048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of Annealing and Temperature on SGOI Fabrication Using Ge Condensation 退火和温度对Ge缩合制备SGOI的影响
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251018
S. Balakumar, C.S. Ongu, C. Tung, A. Trigg, M. Li, R. Kumar, G. Lo, N. Balasubramanian, Y. Yeo, D. Kwong
{"title":"Effects of Annealing and Temperature on SGOI Fabrication Using Ge Condensation","authors":"S. Balakumar, C.S. Ongu, C. Tung, A. Trigg, M. Li, R. Kumar, G. Lo, N. Balasubramanian, Y. Yeo, D. Kwong","doi":"10.1109/IPFA.2006.251018","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251018","url":null,"abstract":"In this work, we investigate the effects of oxidation temperature and annealing on Ge movement, and amorphization as an undesirable consequence of inappropriate lowering of temperature during Ge condensation. Possible mechanisms, solutions and implications are presented and it is shown that SiGe with up to 60% Ge can be obtained with oxidation and annealing at a high temperature of 1050degC","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114426904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Using Probing Techniques to Identify and Study High Leakage Issues in the Development of 90nm Process and Below 利用探测技术识别和研究90纳米及以下工艺开发中的高泄漏问题
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.250997
E. Hendarto, Z. Mai, P. K. Tan, A. Lek, B. Lau, J. Lam, W. Chim
{"title":"Using Probing Techniques to Identify and Study High Leakage Issues in the Development of 90nm Process and Below","authors":"E. Hendarto, Z. Mai, P. K. Tan, A. Lek, B. Lau, J. Lam, W. Chim","doi":"10.1109/IPFA.2006.250997","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250997","url":null,"abstract":"The combined use of scanning probe microscope based techniques, namely conductive atomic force microscopy (C-AFM) and tunneling atomic force microscopy (TUNA), and nanoprobing technique is presented. In 90 nm process and below, C-AFM identifies leakage by current mapping, while TUNA measures the current-voltage (I-V) curves of different contacts to study the integrity of individual contacts. Nanoprobing is used to obtain and compare the I-V characteristics of good and leaky transistors","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129487501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The Quantitative Analysis Methodology of Charged Potential by Electron Beam Bombardment for Improving the Passive Voltage Contrast on Advanced Technology 改进无源电压对比的电子束轰击带电电位定量分析方法
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251028
Y.R. Chen
{"title":"The Quantitative Analysis Methodology of Charged Potential by Electron Beam Bombardment for Improving the Passive Voltage Contrast on Advanced Technology","authors":"Y.R. Chen","doi":"10.1109/IPFA.2006.251028","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251028","url":null,"abstract":"Passive voltage contrast (PVC) using electron beam (E-beam) is the popular technique of the failure analysis procedure of real integrated circuit (IC) products. When the sample is exposed on the different energy electron beam, the surface of sample is charged positively or negatively. The charging characteristic is dependent on the secondary electron yield, but that is just qualitative analysis of charging voltage using electron beam. Because of the advancement of technology, shrinking of device and lower operation voltage, the potential that the charge induced using electron beam must be considered. This methodology described in this paper is how to quantify the charging voltage when we applied the passive voltage contrast using low energy electron beam or high energy electron beam. Based on that, we can judge if the gate was turned on by this charged potential and the passive voltage contrast will be used more efficiently, especially for the soft defect on the front-end","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129732509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology 65纳米块体CMOS工艺中栅极-硅化和栅极-非硅化、漏极/源极-硅化阻流ESD nmosfet失效机理分析
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251045
J. Li, D. Alvarez, K. Chatty, M. Abou-Khalil, R. Gauthier, C. Russ, C. Seguin, R. Halbach
{"title":"Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology","authors":"J. Li, D. Alvarez, K. Chatty, M. Abou-Khalil, R. Gauthier, C. Russ, C. Seguin, R. Halbach","doi":"10.1109/IPFA.2006.251045","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251045","url":null,"abstract":"Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the silicide-blocked drain/source and the polysilicon gate is avoided. For 2.5V thick oxide devices, drain-to-substrate junction shorting was observed, whereas, for 1.0V thin oxide devices, gate-oxide breakdown failure occurred","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126005587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Breakthroughs in the Analysis of Leakage Failures in PBGA Packages PBGA封装泄漏失效分析的突破
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251039
D. Campos, M. Bailon, R.J. Camat, R.M. Gozun, R. Manay, F. Somera
{"title":"Breakthroughs in the Analysis of Leakage Failures in PBGA Packages","authors":"D. Campos, M. Bailon, R.J. Camat, R.M. Gozun, R. Manay, F. Somera","doi":"10.1109/IPFA.2006.251039","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251039","url":null,"abstract":"In the event of leakage failures in plastic ball grid array packages (PBGA), standard failure analysis procedure includes acid etching (called decapsulation) of the mold compound to expose the die. Those that are recovering after decapsulation were just closed as a random event caused by a foreign material (FM) in the mold compound. The need to determine the actual defect, which was suspected to have been removed during decapsulation, prompted other ways of characterizing and understanding the failure other than the standard failure analysis flow. Failure analysis (FA) tools and methods that are normally not utilized for analysis of leakage failures will be showcased here like mechanical grinding of mold compound, energy dispersive X-ray (EDX) and conductive atomic force microscopy (C-AFM) analyses. In this paper, we would like to present how we used these tools to find the defect, to fully characterize it and to use the data for rootcausing efforts","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133906012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Trapped Charge Distribution during the P/E Cycling of SONOS Memory SONOS存储器P/E循环过程中的捕获电荷分布
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251003
H. Pang, L. Pan, Lei Sun, Dong Wu, Jun Zhu
{"title":"Trapped Charge Distribution during the P/E Cycling of SONOS Memory","authors":"H. Pang, L. Pan, Lei Sun, Dong Wu, Jun Zhu","doi":"10.1109/IPFA.2006.251003","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251003","url":null,"abstract":"Two phases during the P/E cycling of 0.18mum SONOS are observed using a combined charge pumping method to extract the trapped charge distribution: holes accumulation at the initial term, and electrons accumulation after long term cycling. Better endurance characteristic is obtained through optimization to P/E condition and process technology","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132565605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Non-Volatile Memory Technology-Today and Tomorrow 非易失性存储器技术——今天和未来
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.250989
Chih-Yuan Lu, T. Lu, Rich Liu
{"title":"Non-Volatile Memory Technology-Today and Tomorrow","authors":"Chih-Yuan Lu, T. Lu, Rich Liu","doi":"10.1109/IPFA.2006.250989","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250989","url":null,"abstract":"Despite strong scaling limitations for both NOR and NAND flash memories, solutions to continue the Moore's law are also emerging. For NOR flash memory, 2-bit/cell NROM, BE-SONOS and phase-change chalcogenide memory show promise to scale below 35nm node. For NAND flash memory, new nitride storage devices such as TANOS and BE-SONOS are candidates for < 30 nm devices","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122100805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Modeling of the Leakage Current in Ultrathin La2O3 Films Using a Generalized Power Law Equation 用广义幂律方程模拟超薄La2O3薄膜中的泄漏电流
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251051
E. Miranda, H. Iwai
{"title":"Modeling of the Leakage Current in Ultrathin La2O3 Films Using a Generalized Power Law Equation","authors":"E. Miranda, H. Iwai","doi":"10.1109/IPFA.2006.251051","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251051","url":null,"abstract":"The leakage current in electrically stressed MOS structures with ultrathin lanthanum oxide (La2O3) films was investigated. The samples were obtained by the electron-beam evaporation technique and annealed in-situ in ultra-high vacuum conditions. We show that the application of successive voltage ramps leads to a set of current-voltage (I-V) characteristics that can be simulated using a power-law model with series and parallel resistances. This particular voltage dependence, in combination with the stepwise increase exhibited by the current-time (I-t) characteristic during a constant voltage stress, suggests that the leakage current through the oxide layer might be ascribed to multiple dielectric breakdown conduction","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124822913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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