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2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

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Detectivity Optimization of InGaAs Photon Emission Microscope Systems InGaAs光子发射显微镜系统的探测性优化
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251053
S.L. Tan, K. Yim, D.S.H. Chan, J. Phang, Y. Zhou, L. Balk, C. Chua, L. S. Koh
{"title":"Detectivity Optimization of InGaAs Photon Emission Microscope Systems","authors":"S.L. Tan, K. Yim, D.S.H. Chan, J. Phang, Y. Zhou, L. Balk, C. Chua, L. S. Koh","doi":"10.1109/IPFA.2006.251053","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251053","url":null,"abstract":"Although photon emission microscope (PEM) systems are widely used in integrated circuit failure analysis, there is no known quantitative baseline to assess and compare the overall sensitivity performance of PEM systems. This paper describes a method to quantify the overall sensitivity of PEM systems based on spectral detectivity measurements. It has been applied to HgCdTe (MCT) and InGaAs PEM systems. It is also applied to an InGaAs PEM system to quantify the change in the detectivity of the InGaAs PEM system as the temperature of the detector changes. The method is also used to compare the signal to noise ratio of an emission image by normal time integration with digital integration where many frames of an emission image is added up to produce a single emission image","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127449359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Local Strained Channel (LSC) nMOSFETs by Different Poly-Si Gate and SiN Capping Layer Thicknesses: Mobility Enhancement, Size Dependence, and Hot Carrier Stress 不同多晶硅栅极和SiN封盖层厚度的局部应变通道(LSC) nmosfet:迁移率增强，尺寸依赖性和热载流子应力
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251004
Yao-Jen Lee, C. Fan, Wen-Luh Yang, Wenbo Lin, Bohr‐Ran Huang, T. Chao, D. Chuu
{"title":"Local Strained Channel (LSC) nMOSFETs by Different Poly-Si Gate and SiN Capping Layer Thicknesses: Mobility Enhancement, Size Dependence, and Hot Carrier Stress","authors":"Yao-Jen Lee, C. Fan, Wen-Luh Yang, Wenbo Lin, Bohr‐Ran Huang, T. Chao, D. Chuu","doi":"10.1109/IPFA.2006.251004","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251004","url":null,"abstract":"In this study, we propose a LSC technique that using SiN capping layer deposition with high mechanical stress on single poly-Si gate. In addition, nMOSFETs with thicker poly-Si gate (220 nm) can also increase tensile strain in the channel region compared to that of the thinner (150nm) poly-Si gate structure. Furthermore, size dependence of nMOSFETs with SiN capping layer is also studied and compared the thickness of SiN and poly-Si gate simultaneously. In the final, reliability of hot carrier injection is studied for all splits (Songlp, 1992). The trend of degradation among the splits of SiN capping layer is abnormal to the tensile stress on the channel","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"C-24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126477427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of FIB-based Charge Reduction Methods for Auger Electron Spectroscopy and Their Application in Failure Analysis 基于fib的俄歇电子能谱电荷还原方法的发展及其在失效分析中的应用
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.250999
R. R. Nistala, C. Tan, Y. Hua, S.P. Zhao
{"title":"Development of FIB-based Charge Reduction Methods for Auger Electron Spectroscopy and Their Application in Failure Analysis","authors":"R. R. Nistala, C. Tan, Y. Hua, S.P. Zhao","doi":"10.1109/IPFA.2006.250999","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250999","url":null,"abstract":"Surface charging is encountered in the study Auger electron spectroscopy of non-conducting surfaces. In this paper, two case studies of (i) Au-pad of packaged die unit and (ii) floating Al-pads of patterned wafer were presented. Surface charging was noticed in both the samples and it was not possible to eliminate the effect with convention charge reduction methods. Two FIB-based methods of charge reduction with potential applications in a failure analysis lab were discussed. The essence of techniques is to provide conducting path to charge accumulated on the surface of specimen. This is achieved by drawing Pt wires using FIB technique. In one of the methods discussed, Pt wire is deposited and patterned in the vicinity of feature of interest while, in the second technique a hole is drilled to Si substrate using a laser source and followed by Pt deposition. Both the methods were effective in reducing surface charge, thus aiding in Auger data collection","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126493751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of EDS Technique for OSP Film Thickness Measurement EDS技术在OSP膜厚测量中的应用
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251030
K. Prong, K. Sirarat
{"title":"Application of EDS Technique for OSP Film Thickness Measurement","authors":"K. Prong, K. Sirarat","doi":"10.1109/IPFA.2006.251030","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251030","url":null,"abstract":"Nowadays, there are numbers of pad finishing types in market for ball grid array package (BGA). OSP (organic solderability preservatives) pad finishing technology is one of the most widely used for the purpose of increasing the joint strength and achieving more excellence in heat-resistance. Especially, to develop the ICs products to have compatibility with non-clean soldering fluxes and solder paste as well as lead-free solder, OSP becomes one most suggested. Spansion with the commitment to customer requirements, has to implement OSP pad in our products i.e. FBGA packages. OSP pad is one of pad finishing technologies that Cu pad is coated with the thin film of a kind of organic material to protect Cu from oxidation during storage and many processes in IC manufacturing. The thickness the OSP film coated over Cu layer is in order of micrometer. Normally, during solder ball attachment process OSP will be cleaned out by soldering flux and heat to allow Cu to expose and attach to solder ball. The point is that if the thickness of OSP is too thin (less than 0.12 micron), the film cannot prevent copper from oxidation during storage and heat cycles. On the other hand, if the OSP film is too thick (more than 0.4 micron), OSP will not be perfectly cleaned out by flux during soldering reflow process. Hence this will bring to the bad solder joint because the presence of some OSP residue can result in bad solder wetting. This can affect on the attachment of solder ball and finally lead to significantly weak solder joint. Therefore, thickness of OSP film is one of the most critical factors that we have to consider and control in order to achieve desirable joint strength. Without OSP thickness information we will be unable to be confident in the quality of our product and unable to control incoming quality of substrate from supplier site. So, it is highly necessary to measure the OSP thickness or at least for monitoring and analysis purposes","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121172234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel method for debug of electrostatic discharge protection in VLSI circuits VLSI电路静电放电保护调试的新方法
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251043
S. Sofer, Y. Fefer, M. Borenshtein, Y. Shapira
{"title":"Novel method for debug of electrostatic discharge protection in VLSI circuits","authors":"S. Sofer, Y. Fefer, M. Borenshtein, Y. Shapira","doi":"10.1109/IPFA.2006.251043","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251043","url":null,"abstract":"A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"98 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131624437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Standard Silicon CMOS Device uses for developing a Biological Sensor 用于开发生物传感器的标准硅CMOS器件
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251047
E. Volynsky, E. Frenkel-Ben-Yakar, Y. Sternberg
{"title":"Standard Silicon CMOS Device uses for developing a Biological Sensor","authors":"E. Volynsky, E. Frenkel-Ben-Yakar, Y. Sternberg","doi":"10.1109/IPFA.2006.251047","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251047","url":null,"abstract":"Antibody/antigen concept biological sensors as presented in D. Diamond (1998) have shown a very impressive growth in the last decade due to their high selectivity to specific biomolecules. They can allow fast and early detection of various kinds of illnesses and infections. One of the main challenges in this field is to develop biosensors that can be easily inserted within the human body and act as \"illness or body malfunction detectors\" by reacting to changes in antibody concentration. An important issue facing researchers in this aspect is to build biosensors as stated in K. Gartsman et al. (1998) by using known and inexpensive technologies presented in D. G. Wu et al. (2000). The use of silicon (Si) is very attractive in this sense due to its low price and high reliability","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127807036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability 具有扇出能力的金属晶片WLCSP技术的析因分析
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251035
M. Yew, C. Yuan, C.N. Han, C.S. Huang, W. Yang, K. Chiang
{"title":"Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability","authors":"M. Yew, C. Yuan, C.N. Han, C.S. Huang, W. Yang, K. Chiang","doi":"10.1109/IPFA.2006.251035","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251035","url":null,"abstract":"In this study, a wafer level chip scaled packaging (WLCSP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the fan-out WLCSP, the solder bumps could be located on both the filler polymer and chip surface. The concept of the fan-out WLCSP and the processes of fabricating the novel fan-out WLCSP would be described. In addition, the reliability characteristic of the fan-out WLCSP in packaging level is described by using the two-dimensional finite element model. The 25 factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124369708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Technology Reliability Qualification of a 65nm CMOS Cu/Low-k BEOL Interconnect 65nm CMOS Cu/Low-k BEOL互连技术可靠性鉴定
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.251007
F. Chen, B. Li, T. Lee, C. Christiansen, J. Gill, M. Angyal, M. Shinosky, C. Burke, W. Hasting, R. Austin, T. Sullivan, D. Badami, J. Aitken
{"title":"Technology Reliability Qualification of a 65nm CMOS Cu/Low-k BEOL Interconnect","authors":"F. Chen, B. Li, T. Lee, C. Christiansen, J. Gill, M. Angyal, M. Shinosky, C. Burke, W. Hasting, R. Austin, T. Sullivan, D. Badami, J. Aitken","doi":"10.1109/IPFA.2006.251007","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251007","url":null,"abstract":"During the development and qualification of a 300mm low-k/Cu back end of line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for 65nm Cu/low-k interconnects is reported and various reliability issues associated with process integration and material optimization during initial development stage are discussed. Finally, we demonstrate that with careful process and materials optimization, a superior interconnect reliability performance at the 65nm technology node can be achieved for 300mm fabrication. The projected reliability lifetimes of TDDB, EM, and SM meet the most stringent reliability targets and criteria","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"17 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132571122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Impact of Random Bit Values on NBTI Lifetime of an SRAM Cell 随机位值对SRAM单元NBTI寿命的影响
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.250993
R. Wittmann, H. Puchner, H. Ceric, S. Selberherr
{"title":"Impact of Random Bit Values on NBTI Lifetime of an SRAM Cell","authors":"R. Wittmann, H. Puchner, H. Ceric, S. Selberherr","doi":"10.1109/IPFA.2006.250993","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250993","url":null,"abstract":"Companies estimate the NBTI lifetime of SRAM memories usually by extrapolation of the DC degradation. This method underestimates the lifetime of the memory cell since the bit change in the cell over time is neglected. In this work we have analyzed the impact of storing random bit values in a 6T-SRAM memory cell by using probabilities of storing a one bit between the boundaries of 100% (fully unsymmetric stress) and 50% (symmetric stress). It turned out that the SRAM lifetime for using an unsymmetry of 90% in the stress-split between T2 and T4 is 1.14 times longer than the DC lifetime. We have also demonstrated that the NBTI degradation of the cell converges to the DC degradation for highly unsymmetric stress levels with a probability of over 90% for a one bit. It turned out that the calibrated reaction-diffusion model is useful to study the NBTI response not only for driving the gate with periodic rectangular signals but also for storing random bit sequences in an SRAM cell","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123979516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A novel empirical model for NBTI recovery with the modulated measurement time frame 一个具有调制测量时间框架的NBTI恢复的新经验模型
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI: 10.1109/IPFA.2006.250991
J.B. Yang, T.P. Chen, S. Tan, L. Chan
{"title":"A novel empirical model for NBTI recovery with the modulated measurement time frame","authors":"J.B. Yang, T.P. Chen, S. Tan, L. Chan","doi":"10.1109/IPFA.2006.250991","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250991","url":null,"abstract":"Negative bias temperature instability (NBTI) of p-MOSFETs gets recovered immediately when the stress is removed, and hence the electrical measurement will tend to underestimate the NBTI degradation due to its unavoidable measurement time. This measurement-induced additional NBTI recovery must also be taken into account, especially during the NBTI recovery process, because it directly affects the time frames. In this work, by using different measurement time interval during the electrical characterization, this repeatable NBTI recovery phenomenon is used to extract the critical measurement time. Thereafter, with the modulated time interval, a novel empirical model for longer-time NBTI recovery is also proposed here so as to describe the entire NBTI recovery process together with previous short-time limited empirical model","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129054723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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