Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability

Abstract

In this study, a wafer level chip scaled packaging (WLCSP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the fan-out WLCSP, the solder bumps could be located on both the filler polymer and chip surface. The concept of the fan-out WLCSP and the processes of fabricating the novel fan-out WLCSP would be described. In addition, the reliability characteristic of the fan-out WLCSP in packaging level is described by using the two-dimensional finite element model. The 25 factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging