VLSI电路静电放电保护调试的新方法

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI:10.1109/IPFA.2006.251043

S. Sofer, Y. Fefer, M. Borenshtein, Y. Shapira

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引用次数: 1

摘要

提出了一种基于实际静电放电应力低能量无损仿真的VLSI电路静电放电保护失效分析与调试方法。它允许在应力期间测量芯片上的电流和电压，提供关于保护方法正常运行或故障原因的直接和明确的结论

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Novel method for debug of electrostatic discharge protection in VLSI circuits

A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure

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2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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