2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

{"title":"Diffractive lenses for high resolution laser based failure analysis","authors":"F. Zachariasse, M. Goossens","doi":"10.1109/IPFA.2006.251006","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251006","url":null,"abstract":"In this paper, we demonstrate a practical alternative to the conventional SIL, which overcomes the above limitations. We show that it is possible to fabricate a lens directly on the back side of the silicon of the device under test. This lens works on principles of diffractive optics and is around 250 nm thick. The lens may be fabricated in about 1 hour, using a combination of FIB ion implantation lithography, followed by plasma etching. In combination with a commercial IR microscope objective, the lens shows diffraction-limited resolution as expected from its numerical aperture. It should be noted that the lens works only for monochromatic light, but this is not a drawback when applied to laser based techniques","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133227337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-Classical Hot-Electron Gate Current in the Deep Submicrometer N-MOS Flash Memory Cell","authors":"Y. Zhang, D. Ang, H.P. Kuan, K. Tan","doi":"10.1109/IPFA.2006.251001","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251001","url":null,"abstract":"In this paper, experimental features of a non-classical hot-electron gate current I_g ^e obtained under V_b = 0, similar to those reported earlier under reverse V_b are presented. To the best of our knowledge, this is the first direct observation of this non-classical I_g ^e component in deep submicrometer N-channel MOSFET under conventional CHE biasing, i.e. when V_g ap V_d and V_b = 0. Based on the results, a phenomenological explanation as well as some further supporting experimental evidence is also presented here","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129510835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic Optical Techniques for IC Debug and Failure Analysis","authors":"J. Ferrigno, R. Desplats, P. Perdu, K. Sanchez, F. Beaudoin, D. Lewis","doi":"10.1109/IPFA.2006.250980","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250980","url":null,"abstract":"Optical techniques (light emission and laser stimulation techniques) are routinely used for precise IC defect localization. At the early stage of an analysis, choosing the right technique is an increasingly complex task. In some cases, one technique may bring value but no the others. Using an 180nm test structure device we present results showing the complementary of emission microscopy (EMMI), time-resolved emission (TRE) and dynamic laser stimulation (DLS) in order to help failure analyists or debug engineers to choose the right approach","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121506266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of Temperature and Strain Rate Behavior of Lead-free Solder Sn96.5Ag3.5","authors":"F. Zhu, H. Zhang, R. Guan, S. Liu, Y.B. Yang","doi":"10.1109/IPFA.2006.251038","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251038","url":null,"abstract":"In the late years, many countries will begin to prohibit using the lead-based solders in microelectronic packaging processes in view of inherent toxicity of lead-based solder alloys. The waste electrical and electronic equipment (WEEE) directive by EU has claimed that the use of Pb in consumer electronics will be banned after January 2006. Therefore, the development of lead-free solders replacing Pb-containing solders has been a crucial task for academe and microelectronic packaging industry. Due to the formation of fine Ag3Sn inter-metallic compound precipitates, Sn-Ag binary lead-free solders have some good mechanical properties (ductility, creep resistance and thermal resistance), and they were defined promising candidates substituting Pb-containing solders in microelectronic packaging and interconnecting. However, many mechanical properties of Sn-Ag alloys have not been clarified because Sn-Ag solder alloys used in microelectronic interconnecting process have not a long history. As the interconnecting materials in microelectronic packaging processes, mechanical properties of soldering alloys are important parts to impact the packaging quality, and determine the fracture and thermal fatigue behaviors of solder joint. Recently the trend of higher circuit board component densities results in the decrease of microelectronic packaging dimensions and the solder bump sizes. Therefore, the requirements for mechanical characteristics of lead-free solders will be more rigorous in packaging process. Thus, the research work about the mechanical properties of Sn-Ag binary solders is essential to microelectronic industry and academe. During microelectronic components and devices operating, the packaging and interconnecting materials would be subjected to the thermal-mechanical stress and strain which could affect the reliability and life of microelectronic components. Thus, in this study, it was focused on researching thermal-mechanical properties of the lead-free solder alloy Sn96.5Ag3.5 at different temperature ranging from 25 degC to 125 degC and various strain rate ranging from 10-5 S-1 to 10-1 S-1. Morphology of rupture surface and microstructure of this lead-free solder Sn96.5Ag3.5 were also analyzed by using the scanning electron microscope (SEM)","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127285987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Review of New Characterization Methodologies of Gate Dielectric Breakdown and Negative Bias Temperature Instability","authors":"M. A. Alam","doi":"10.1109/IPFA.2006.250990","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250990","url":null,"abstract":"In this paper, we discuss the physical principles of set of new measurement techniques to explore the reliability limits of (time dependent) dielectric breakdown (TDDB) and negative bias temperature instability (NBTI), two major reliability concerns of high performance logic/memory transistors. Our analysis of the techniques provides a sound theoretical foundation of the measurement algorithms. This analysis can be used to explore the limitations of the techniques in a systematic way and find innovative solutions to address the limitations. Such systematic studies and gradual adoption of the new measurement techniques by Equipment companies and Standards Committees would eventually allow integration of the new measurement techniques to standard methodologies available for device and process characterization","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116803575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Study of Sulphur Assisted Corrosion in Technologies with Copper Interconnects","authors":"N. Kamat, M. Lai, Oh Chong Khiam, Li Kun","doi":"10.1109/IPFA.2006.251026","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251026","url":null,"abstract":"Increased packing density and reduced device size leads to increase in the back-end related delays. This happens as a result of increase in the metal resistance due to decreased line-width and increased capacitance due to a higher density of the interconnects. To minimize the impact of interconnect related delays (RC delay) the semiconductor industry had to, as a first order change, look for metal with a lower sheet resistance. Copper being material with lower sheet resistance, was chosen for the interconnect purposes. In the dual damascene approach to copper interconnect patterning, capping of copper after the copper CMP process is very important. It is well know that copper, when exposed to air, corrodes. Different types of copper corrosion phenomena are described in literature. Copper also diffuses into the dielectric causing shorts or leakages between the adjacent metal lines. A Si3N4 or SiC capping layer is, therefore, deposited almost immediately after the copper CMP process. These dielectric capping layers are found to be good barriers for copper diffusion/corrosion. In a manufacturing environment, it is practically impossible to cap the freshly exposed copper surface, immediately, by depositing the dielectric barrier due to time constraint. Batches of wafer are kept in a neutral ambient like the N2 ambient, to prevent copper corrosion from happening, before the dielectric barrier deposition. After careful study, a time-link is established between the deposition of the dielectric barrier and the copper CMP process. The dielectric barrier is supposed to be deposited within the time established by the \"time-link\" to prevent the copper from corroding. In this paper, a new copper corrosion mechanism is reported which is found to be sulphur assisted","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121615686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inductance Considerations of on-Chip Interconnections for Best Electrostatic Discharge Protection Performance","authors":"S. Sofer, Y. Fefer, Y. Shapira","doi":"10.1109/IPFA.2006.251020","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251020","url":null,"abstract":"The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125709973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gate-Oxide Reliability on CMOS Analog Amplifiers in a 130-nm Low-Voltage CMOS Processes","authors":"Jung-Sheng Chen, M. Ker","doi":"10.1109/IPFA.2006.250994","DOIUrl":"https://doi.org/10.1109/IPFA.2006.250994","url":null,"abstract":"The effect of gate-oxide reliability in MOSFET on common-source amplifiers is investigated with the non-stacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain, unity-gain frequency, and output DC voltage level under DC stress and AC stress with DC offset, respectively. The small-signal parameters of amplifier with non-stacked structure strongly degrade under such overstress conditions. The gate-oxide reliability in analog circuit can be improved by stacked structure for small-signal input and output applications","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130448261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-k Dielectric Breakdown Improvement with Co(W,P) Cap Barrier","authors":"T. L. Tan, J. Gan, C. Gan, N. Hwang, J. Gambino","doi":"10.1109/IPFA.2006.251008","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251008","url":null,"abstract":"In summary, the implementation of a Co(W,P) cap only on the Cu lines is able to improve the dielectric breakdown performance in Cu/low-k interconnects. This is due to the elimination of the weak interface between the cap and the low-k dielectric. However, the thickness of the Co(W,P) cap needs to be optimized in order to fully benefit from the breakdown improvement while maintaining its efficiency as a Cu diffusion barrier. The leakage mechanism for the SiN cap is deduced to be Poole-Frenkel emission while the leakage mechanism for the Co(W,P) cap is likely to be Schottky emission","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116688984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lead frame Hillock-Induced Silicon Crack","authors":"R. Flores, M. Fabia, M.T. Nabong, A. Soria, C.B. Gabunas","doi":"10.1109/IPFA.2006.251040","DOIUrl":"https://doi.org/10.1109/IPFA.2006.251040","url":null,"abstract":"End customer in circuit test rejects at a rate of 2-5% was sent back to manufacturer for analysis and inspection. Electrical failure analysis had revealed some leakage on particular pin not included in the production test program. Physical failure analysis on those parts revealed micro-crack on affected pins. The micro cracks were found to be within the bonding vicinity and shown to have been propagating downwards into the silicon chip. The root cause was identified to be hillock on lead frame. Hillocks are formed on the surface of a lead frame during the rolling process of its base metal. Roller's surface irregularities and foreign materials on them could scrape the metal's surface. The scraped material's termination point will then produce an accumulated metal higher than the base surface. To sum up, the lead frame will produce tiny copper spikes on the surface which may cause a potential problem on IC packaging. Presence of these hillocks can cause a serious effect especially when its height already touches the surface of chip backside causing high stresses during wire bonding process. The work presents a new silicon crack mechanism and introduces stress modeling as a good validation tool in search for the root cause","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123296623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}