130纳米低压CMOS工艺中CMOS模拟放大器的栅极-氧化物可靠性

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI:10.1109/IPFA.2006.250994

Jung-Sheng Chen, M. Ker

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引用次数: 3

摘要

在130纳米低压CMOS工艺中，采用非堆叠和堆叠两种结构研究了MOSFET栅极氧化物可靠性对共源放大器的影响。在放大器上施加2.5 V的电源电压，加速观察栅极氧化物可靠性对电路性能的影响，包括在直流应力和直流偏置的交流应力下的小信号增益、单位增益频率和输出直流电压水平。在这种超应力条件下，非堆叠结构放大器的小信号参数严重退化。在小信号输入输出应用中，采用堆叠结构可以提高模拟电路的栅氧化可靠性

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Gate-Oxide Reliability on CMOS Analog Amplifiers in a 130-nm Low-Voltage CMOS Processes

The effect of gate-oxide reliability in MOSFET on common-source amplifiers is investigated with the non-stacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain, unity-gain frequency, and output DC voltage level under DC stress and AC stress with DC offset, respectively. The small-signal parameters of amplifier with non-stacked structure strongly degrade under such overstress conditions. The gate-oxide reliability in analog circuit can be improved by stacked structure for small-signal input and output applications

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2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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