片上互连的电感考虑以获得最佳静电放电保护性能

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2006-07-03 DOI:10.1109/IPFA.2006.251020

S. Sofer, Y. Fefer, Y. Shapira

{"title":"片上互连的电感考虑以获得最佳静电放电保护性能","authors":"S. Sofer, Y. Fefer, Y. Shapira","doi":"10.1109/IPFA.2006.251020","DOIUrl":null,"url":null,"abstract":"The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Inductance Considerations of on-Chip Interconnections for Best Electrostatic Discharge Protection Performance\",\"authors\":\"S. Sofer, Y. Fefer, Y. Shapira\",\"doi\":\"10.1109/IPFA.2006.251020\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design\",\"PeriodicalId\":283576,\"journal\":{\"name\":\"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-07-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2006.251020\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2006.251020","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

在静电放电(ESD)应力作用下，片上互连线的电感会引起电压谐振效应。沿不同ESD电流路径的谐振振荡的相位差产生了显著的局部瞬时电压。有关该电感的信息使设计人员能够在ESD保护设计中考虑这些电压谐振效应

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Inductance Considerations of on-Chip Interconnections for Best Electrostatic Discharge Protection Performance

The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits

自引率

0.00%

发文量