Twin- gd:一种新的双门二极管测量方法,用于EOT低至1nm的超薄栅氧化MOSFET的界面表征

G.D. Lee, S.S. Chung, A. Mao, W. Lin, C.W. Yang, Y. S. Hsieh, K. Chu, L. W. Cheng, H. Tai, L. T. Hsu, C.R. Lee, H. Meng, C. Tsai, G. H. Ma, S. Chien, S. Sun
{"title":"Twin- gd:一种新的双门二极管测量方法,用于EOT低至1nm的超薄栅氧化MOSFET的界面表征","authors":"G.D. Lee, S.S. Chung, A. Mao, W. Lin, C.W. Yang, Y. S. Hsieh, K. Chu, L. W. Cheng, H. Tai, L. T. Hsu, C.R. Lee, H. Meng, C. Tsai, G. H. Ma, S. Chien, S. Sun","doi":"10.1109/IPFA.2006.250992","DOIUrl":null,"url":null,"abstract":"In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1 nm (EOT). With the scaling of gate oxide thickness into 1 nm regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT= 10.2Aring) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Twin-GD: A New Twin Gated-Diode Measurement for the Interface Characterization of Ultra-Thin Gate Oxide MOSFET's with EOT Down to 1nm\",\"authors\":\"G.D. Lee, S.S. Chung, A. Mao, W. Lin, C.W. Yang, Y. S. Hsieh, K. Chu, L. W. Cheng, H. Tai, L. T. Hsu, C.R. Lee, H. Meng, C. Tsai, G. H. Ma, S. Chien, S. Sun\",\"doi\":\"10.1109/IPFA.2006.250992\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1 nm (EOT). With the scaling of gate oxide thickness into 1 nm regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT= 10.2Aring) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide\",\"PeriodicalId\":283576,\"journal\":{\"name\":\"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-07-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2006.250992\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2006.250992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种新的双栅极二极管(T-GD)方法,用于MOS器件的氧化界面表征,其栅极氧化物厚度为1nm (EOT)。当栅极氧化层厚度按比例缩小到1nm时,由于栅极隧穿漏电流的存在,已有的GD测量结果无法给出正确的测量结果。这里,我们提供了一个简单的方法来消除这个限制。该方法已成功地用于超薄(EOT= 10.2Aring)栅氧化nMOSFET器件。并证明了该方法在高k栅介电器件的PBTI效应中的应用。研究发现,高k器件栅极氧化物质量较差,但其界面损伤小于对照氧化物
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Twin-GD: A New Twin Gated-Diode Measurement for the Interface Characterization of Ultra-Thin Gate Oxide MOSFET's with EOT Down to 1nm
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1 nm (EOT). With the scaling of gate oxide thickness into 1 nm regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT= 10.2Aring) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信