D. Lachenal, Y. Rey-Tauriac, L. Boissonnet, B. Reynard, A. Bravaix
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引用次数: 2
Abstract
This paper presents reliability investigations in NLDEMOS transistor in 0.13μm SOI CMOS technology. Reliability tests under hot carrier injections (HCI) for different gate-lengths show two different degradation mechanisms. The modification of current path with short overlap (Olap) due to oblique equi-potential lines and the increase in the vertical electrical field under the gate edge at low V g lead to distinguish Nit interface trap generation from the source side injection