G.D. Lee, S.S. Chung, A. Mao, W. Lin, C.W. Yang, Y. S. Hsieh, K. Chu, L. W. Cheng, H. Tai, L. T. Hsu, C.R. Lee, H. Meng, C. Tsai, G. H. Ma, S. Chien, S. Sun
{"title":"Twin-GD: A New Twin Gated-Diode Measurement for the Interface Characterization of Ultra-Thin Gate Oxide MOSFET's with EOT Down to 1nm","authors":"G.D. Lee, S.S. Chung, A. Mao, W. Lin, C.W. Yang, Y. S. Hsieh, K. Chu, L. W. Cheng, H. Tai, L. T. Hsu, C.R. Lee, H. Meng, C. Tsai, G. H. Ma, S. Chien, S. Sun","doi":"10.1109/IPFA.2006.250992","DOIUrl":null,"url":null,"abstract":"In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1 nm (EOT). With the scaling of gate oxide thickness into 1 nm regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT= 10.2Aring) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide","PeriodicalId":283576,"journal":{"name":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2006.250992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1 nm (EOT). With the scaling of gate oxide thickness into 1 nm regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT= 10.2Aring) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide