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2007 IEEE Symposium on VLSI Circuits最新文献

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A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue 一种9b、1.25ps分辨率粗精时间-数字转换器，用于放大时间残留
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342701
Minjae Lee, A. Abidi
{"title":"A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue","authors":"Minjae Lee, A. Abidi","doi":"10.1109/VLSIC.2007.4342701","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342701","url":null,"abstract":"A 9 b 1.25 ps two step time-to-digital converter is implemented in 90 nm CMOS. It uses a new circuit to amplify the time residue, and compensates mismatch with subrange normalization. DNL and INL are, respectively, plusmn0.8 LSB and plusmn2 LSB. It can be used as a phase detector with digital output.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"144 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129568053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 120
A 0.5V 8bit 10Msps Pipelined ADC in 90nm CMOS 一个0.5V 8bit 10Msps的90纳米CMOS流水线ADC
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342715
Junhua Shen, P. Kinget
{"title":"A 0.5V 8bit 10Msps Pipelined ADC in 90nm CMOS","authors":"Junhua Shen, P. Kinget","doi":"10.1109/VLSIC.2007.4342715","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342715","url":null,"abstract":"A true low voltage 0.5 V 8 bit pipelined A/D converter is realized in 90 nm CMOS technology using regular Vtau devices. A cascaded sampling technique is used to combat the OFF leakage of the switches. The converter prototype occupies 0.85 mm2; operating at 10 Msps, it consumes 2.4 mW and achieves an SNDR of 48.1 dB with a 0.4 Vppdiff full-scale input.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125972861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A CMOS Readout Circuit for Silicon Resonant Accelerometer with 32-ppb bias stability 一种32 ppb偏置稳定硅谐振加速度计的CMOS读出电路
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342692
Lin He, Y. Xu, M. Palaniapan
{"title":"A CMOS Readout Circuit for Silicon Resonant Accelerometer with 32-ppb bias stability","authors":"Lin He, Y. Xu, M. Palaniapan","doi":"10.1109/VLSIC.2007.4342692","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342692","url":null,"abstract":"This paper describes a fully-differential CMOS readout circuit for silicon micro-resonant accelerometer. Tested with a SOI resonator, the readout chip sustains the oscillation at 110 kHz with a phase noise of -36 dBc@1 Hz and a bias stability of 0.0035 Hz or 32 ppb, which can be translated to an amplitude noise of 1 Aring/radicHz down to 0.05 Hz and stability of 0.22 Aring up to 100 seconds. The chip is fabricated in a 0.35-mum CMOS process and draws 5 mA under a 3.3-V single supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122214271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning 一个完全集成的36MHz到230MHz乘法DLL与自适应电流调谐
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342730
Keng-Jan Hsiao, Tai-Cheng Lee
{"title":"A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning","authors":"Keng-Jan Hsiao, Tai-Cheng Lee","doi":"10.1109/VLSIC.2007.4342730","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342730","url":null,"abstract":"A multiplying-DLL based frequency synthesizer with a fully-integrated loop capacitor employs an adaptive current adjusting loop to generate a low-jitter clock for LCD panel applications. The measured RMS jitter is 3.5 ps for 229.5-MHz output clock. The frequency synthesizer occupies 0.09 mm2 active area in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123911276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A High-Resolution Low-Power Oversampling ADC with Extended-Range for Bio-Sensor Arrays 一种用于生物传感器阵列的高分辨率低功耗过采样ADC
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342736
Ali Agahl, K. Vleugels, Peter B. Griffin, Mostafa Ronaghi, James D. Plummer, B. Wooley
{"title":"A High-Resolution Low-Power Oversampling ADC with Extended-Range for Bio-Sensor Arrays","authors":"Ali Agahl, K. Vleugels, Peter B. Griffin, Mostafa Ronaghi, James D. Plummer, B. Wooley","doi":"10.1109/VLSIC.2007.4342736","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342736","url":null,"abstract":"A calibration-free, high-resolution ADC designed for bioluminescence sensing employs an extended-counting architecture in which the residual error from a second-order incremental SigmaDelta modulator is encoded using a successive approximation ADC. The ADC has been integrated in 0.18-mum CMOS technology and achieves a dynamic range of 90.1 dB and a peak SNDR of 86.3 dB at a conversion rate of 1MSample/sec with 38 mW power consumption.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126344234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
A 2.4GHz ISM-band digital CMOS wireless transceiver with an intra-symbol adaptively intermittent Rx 一种带有符号内自适应间歇Rx的2.4GHz ism波段数字CMOS无线收发器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342775
H. Ishizaki, K. Nose, M. Mizuno
{"title":"A 2.4GHz ISM-band digital CMOS wireless transceiver with an intra-symbol adaptively intermittent Rx","authors":"H. Ishizaki, K. Nose, M. Mizuno","doi":"10.1109/VLSIC.2007.4342775","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342775","url":null,"abstract":"The first achievement of intra-symbol adaptively intermittent receiver has been developed with an inductor-less LNA by 90-nm digital CMOS, and Rx characteristics have been measured (Rx power: 4.5 mW, BER: 4.1times10-5, received signal intensity: -73 dBm, when Rx is enabled within only 8.2% of a single symbol period) with an on-chip stair-like shaping PA (3rd order harmonics of -40.6 dBc) and a digitally controlled direct RF carrier phase modulator (ACPR<-40 dBc).","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132263193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquilst band 150MS/s的14位分段DEM DAC，在Nyquilst波段的SFDR大于83dB
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342714
Kok Lim Chan, Jianyu Zhu, I. Galton
{"title":"A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquilst band","authors":"Kok Lim Chan, Jianyu Zhu, I. Galton","doi":"10.1109/VLSIC.2007.4342714","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342714","url":null,"abstract":"A segmented DEM technique that allows an efficient tradeoff between encoder complexity and the number of unit current-steering cells enables a 150 MS/s DAC with greater than 83 dB of SFDR across the Nyquist band. The 0.18 mum CMOS IC has an active area of 3 mm2 and dissipates 127 mW.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133584187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 512×8 electrical fuse memory with 15μm2 cells using 8-sq asymmetric fuse and core devices in 90nm CMOS 采用8平方的非对称保险丝和90nm CMOS的核心器件，设计了一种具有15μm2单元的512×8电保险丝存储器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342771
Shine C. Chung, Jiann-Tseng Huang, P. Chen, F. Hsueh
{"title":"A 512×8 electrical fuse memory with 15μm2 cells using 8-sq asymmetric fuse and core devices in 90nm CMOS","authors":"Shine C. Chung, Jiann-Tseng Huang, P. Chen, F. Hsueh","doi":"10.1109/VLSIC.2007.4342771","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342771","url":null,"abstract":"A 15 μm2 cell 4 Kb electrical fuse memory is designed in 90 nm CMOS using core devices only. The N+ 8-sq asymmetric fuses are used to enhance fuse uniformity, reliability, and aggregate electro-migration. High-gain cascade amplifiers sense small resistance differences to achieve a 2.25 V program voltage in 1 mus. A sufficient design window is derived and verified by using on-chip resistance monitor without area overheads.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128992697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit 实现超GHz可合成流处理单元的设计方法
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342761
K. Ueno, H. Murakami, N. Yano, R. Okuda, T. Himeno, T. Kamei, Y. Urakawa
{"title":"A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit","authors":"K. Ueno, H. Murakami, N. Yano, R. Okuda, T. Himeno, T. Kamei, Y. Urakawa","doi":"10.1109/VLSIC.2007.4342761","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342761","url":null,"abstract":"A 7.07 mm2 synthesizable streaming processing unit (SPU) is fabricated in a 65 nm CMOS technology with 8 level copper layers. It is migrated from its original custom design to a synthesizable design to get higher design portability. New features are a new floor plan, height optimized standard cell library, local clock generator cloning and adaptive wire width control. Its logic area is 30% smaller than the full custom designed SPU in the same process generation. Correct functional operation is realized in 4 GHz at 1.4 V.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131667852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues 45nm 2port 8T-SRAM，采用分层复制位线技术，可避免同步读写访问问题
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342740
S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu
{"title":"A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues","authors":"S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu","doi":"10.1109/VLSIC.2007.4342740","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342740","url":null,"abstract":"We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45 nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8 T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128 BLtimes512WL 64Kb 2P-SRAM macro which cell size is 0.597mum2 using these schemes was fabricated by 45 nm LSTP CMOS process.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123156867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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