{"title":"一种32 ppb偏置稳定硅谐振加速度计的CMOS读出电路","authors":"Lin He, Y. Xu, M. Palaniapan","doi":"10.1109/VLSIC.2007.4342692","DOIUrl":null,"url":null,"abstract":"This paper describes a fully-differential CMOS readout circuit for silicon micro-resonant accelerometer. Tested with a SOI resonator, the readout chip sustains the oscillation at 110 kHz with a phase noise of -36 dBc@1 Hz and a bias stability of 0.0035 Hz or 32 ppb, which can be translated to an amplitude noise of 1 Aring/radicHz down to 0.05 Hz and stability of 0.22 Aring up to 100 seconds. The chip is fabricated in a 0.35-mum CMOS process and draws 5 mA under a 3.3-V single supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A CMOS Readout Circuit for Silicon Resonant Accelerometer with 32-ppb bias stability\",\"authors\":\"Lin He, Y. Xu, M. Palaniapan\",\"doi\":\"10.1109/VLSIC.2007.4342692\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a fully-differential CMOS readout circuit for silicon micro-resonant accelerometer. Tested with a SOI resonator, the readout chip sustains the oscillation at 110 kHz with a phase noise of -36 dBc@1 Hz and a bias stability of 0.0035 Hz or 32 ppb, which can be translated to an amplitude noise of 1 Aring/radicHz down to 0.05 Hz and stability of 0.22 Aring up to 100 seconds. The chip is fabricated in a 0.35-mum CMOS process and draws 5 mA under a 3.3-V single supply.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342692\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342692","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS Readout Circuit for Silicon Resonant Accelerometer with 32-ppb bias stability
This paper describes a fully-differential CMOS readout circuit for silicon micro-resonant accelerometer. Tested with a SOI resonator, the readout chip sustains the oscillation at 110 kHz with a phase noise of -36 dBc@1 Hz and a bias stability of 0.0035 Hz or 32 ppb, which can be translated to an amplitude noise of 1 Aring/radicHz down to 0.05 Hz and stability of 0.22 Aring up to 100 seconds. The chip is fabricated in a 0.35-mum CMOS process and draws 5 mA under a 3.3-V single supply.
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