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2007 IEEE Symposium on VLSI Circuits最新文献

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A 5.2Gbps hypertransportTM integrated AC coupled receiver with DFR DC restore 具有DFR直流恢复功能的5.2Gbps超传输集成交流耦合接收器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342755
E. Fang, G. Asada, R. Kumar, S. Hale, M. Leary
{"title":"A 5.2Gbps hypertransportTM integrated AC coupled receiver with DFR DC restore","authors":"E. Fang, G. Asada, R. Kumar, S. Hale, M. Leary","doi":"10.1109/VLSIC.2007.4342755","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342755","url":null,"abstract":"A HyperTransportTM receiver with integrated AC coupling achieves an extended DC input common mode voltage without resorting to AC encoding like 8B10B. The receiver supports all HyperTransportTM Revision 3 (HT3) data rate from 2.4 Gbps to 5.2 Gbps. A decision feedback restore (DFR) method is used to counter baseline wander. The design is implemented in a 65 nm SOI CMOS process.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115499635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Compact eFUSE Programmable Array Memory for SOI CMOS 一种用于SOI CMOS的紧凑型eFUSE可编程阵列存储器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342770
J. Safran, A. Leslie, G. Fredeman, C. Kothandaraman, A. Cestero, Xiang Chen, R. Rajeevakumar, Deok-kee Kim, Y. Li, D. Moy, N. Robson, T. Kirihata, S. Iyer
{"title":"A Compact eFUSE Programmable Array Memory for SOI CMOS","authors":"J. Safran, A. Leslie, G. Fredeman, C. Kothandaraman, A. Cestero, Xiang Chen, R. Rajeevakumar, Deok-kee Kim, Y. Li, D. Moy, N. Robson, T. Kirihata, S. Iyer","doi":"10.1109/VLSIC.2007.4342770","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342770","url":null,"abstract":"Demonstrating a >10X density increase over traditional VLSI fuse circuits, a compact eFUSE programmable array memory configured as a 4 Kb one-time programmable ROM (OTPROM) is presented using a 6.2 mum2 NiSix silicide electromigration ITIR cell in 65 nm SOI CMOS. A 20 mus programming time at 1.5 V is achieved by asymmetrical scaling of the fuse and a shared differential sensing scheme. Having zero process cost adder, eFUSE is fully compatible with standard VLSI manufacturing.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116022217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
AC Power Supply Circuits for Energy Harvesting 用于能量收集的交流电源电路
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342779
J. Wenck, R. Amirtharajah, J. Collier, J. Siebert
{"title":"AC Power Supply Circuits for Energy Harvesting","authors":"J. Wenck, R. Amirtharajah, J. Collier, J. Siebert","doi":"10.1109/VLSIC.2007.4342779","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342779","url":null,"abstract":"Passive energy harvesting from mechanical vibration has wide application in wearable and embedded sensors to complement or replace batteries. Energy harvesting efficiency can be increased by eliminating AC/DC conversion. A test chip demonstrating self-timing, power-on-reset circuitry, and memory for energy harvesting AC voltages has been designed in 180 nm CMOS and tested. Circuit operation is confirmed for supply frequencies between 60 Hz and 1 kHz with power consumption below 130 muW.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114556422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2 Multilevel CBRAM 4F2多电平CBRAM的时间离散电压传感与迭代编程控制
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342708
P. Schrögmeier, M. Angerbauer, Stefan Dietrich, M. Ivanov, Heinz Hönigschmid, C. Liaw, M. Markert, R. Symanczyk, L. Altimime, S. Bournat, G. Muller
{"title":"Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2 Multilevel CBRAM","authors":"P. Schrögmeier, M. Angerbauer, Stefan Dietrich, M. Ivanov, Heinz Hönigschmid, C. Liaw, M. Markert, R. Symanczyk, L. Altimime, S. Bournat, G. Muller","doi":"10.1109/VLSIC.2007.4342708","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342708","url":null,"abstract":"Multilevel read/write circuits developed for a 90 nm, 4F2, 1T1CBJ (1-transistor/1-conductive bridging junction) 4Mb CBRAM core are described for the first time. The design uses an on-pitch time-discrete voltage sensing scheme and employs a bitline (BL) charge balancing reference as well as a self-timed iterative program concept. Random read cycle times ap0.7 mus and random write cycle times ap1.35 mus are achieved.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124333039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 63-GHz voltage-controlled oscillator in 0.18-μm CMOS 63 ghz压控振荡器，0.18 μm CMOS
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342705
H. Hsieh, Liang-Hung Lu
{"title":"A 63-GHz voltage-controlled oscillator in 0.18-μm CMOS","authors":"H. Hsieh, Liang-Hung Lu","doi":"10.1109/VLSIC.2007.4342705","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342705","url":null,"abstract":"A novel circuit topology for the millimeter-wave voltage-controlled oscillators (VCOs) is presented. By employing the admittance-transforming technique, the proposed circuit can sustain fundamental oscillation close to the cut-off frequency of the transistors. Utilizing a standard 0.18-mum CMOS process, a V-band VCO is implemented for demonstration. The fabricated circuit exhibits a frequency tuning range of 670 MHz in the vicinity of 63 GHz. The measured output power and phase noise at 1-MHz offset are -15 dBm and -89 dBc/Hz, respectively. Operated at a 1.8-V supply voltage, the total dc current consumption of the VCO and the output buffers is 55 mA.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131998418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing 具有动态单元偏置的低于600mv、耐波动的65nm CMOS SRAM阵列
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342773
Azeez Bhavnagarwala, Stephen V. Kosonocky, Y. Chan, Kevin Stawiasz, U. Srinivasan, Steve Kowalczyk, Matt Ziegler
{"title":"A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing","authors":"Azeez Bhavnagarwala, Stephen V. Kosonocky, Y. Chan, Kevin Stawiasz, U. Srinivasan, Steve Kowalczyk, Matt Ziegler","doi":"10.1109/VLSIC.2007.4342773","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342773","url":null,"abstract":"Combinations of circuit techniques enabling tolerance to Vtau fluctuations in SRAM cell transistors during read or write operations and significant reductions in minimum operating voltage are reported. Implemented in a 9 Kb times 74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST, these techniques, demonstrate VMIN of 0.58 V and 0.40 V/0.54 V for single and dual VDD implementations respectively. The techniques consume a 10-12% overhead in area, improve performance marginally and also enable over 50% reduction in cell leakage with minimal circuit overhead.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130080371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
18Gb/s Optical IO: VCSEL Driver and TIA in 90nm CMOS 18Gb/s光IO: VCSEL驱动和TIA在90nm CMOS
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342749
A. Kern, A. Chandrakasan, I. Young
{"title":"18Gb/s Optical IO: VCSEL Driver and TIA in 90nm CMOS","authors":"A. Kern, A. Chandrakasan, I. Young","doi":"10.1109/VLSIC.2007.4342749","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342749","url":null,"abstract":"An 18 Gb/s optical data rate is achieved with a commercial GaAs VCSEL by applying rising and falling edge pre-emphasis with a 90 nm CMOS driver. The pre-emphasis pulse shape can be digitally adjusted with time resolution less than one bit period. The TIA receiver has cross-coupled cascodes to increase the amplifier gain/bandwidth and operates at 12.5 Gb/s to 18 Gb/s depending on the input capacitance.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131561789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 9Onm CMOS 0.28mm2 1V 12b 40MS/s ADC with 0.39pJ/Conversion-Step 9Onm CMOS 0.28mm2 1V 12b 40MS/s ADC，转换步长0.39pJ
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342713
Kang-Jin Lee, Eunsu Shin, Hee-Suk Yang, Ju-Hwa Kim, Pil-Un Ko, Il-Ryong Kim, Seunghoon Lee, Kyoung-Ho Moon, Jae-Whui Kim
{"title":"A 9Onm CMOS 0.28mm2 1V 12b 40MS/s ADC with 0.39pJ/Conversion-Step","authors":"Kang-Jin Lee, Eunsu Shin, Hee-Suk Yang, Ju-Hwa Kim, Pil-Un Ko, Il-Ryong Kim, Seunghoon Lee, Kyoung-Ho Moon, Jae-Whui Kim","doi":"10.1109/VLSIC.2007.4342713","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342713","url":null,"abstract":"A 1V 12b 40MS/s pipelined ADC using a proposed two stage folded cascaded opamp for low voltage and a proposed frequency compensation technique for fast settling achieves a FOM of 0.39pJ/conversion-step. The prototype ADC implemented in a 90nm digital CMOS process with an active die area of 0.28mm2 consumes 16mW from a 1V power supply. It shows 62dB SNDR and 73dB SFDR for a 5 MHz input at a 40MHz sampling clock.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131787480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 200-μV/e- CMOS image sensor with 100-ke- full well capaclty 一种200 μ v /e的CMOS图像传感器，具有100克满阱容量
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342690
S. Adachi, Woonghee Lee, N. Akahane, H. Oshikubo, K. Mizobuchi, S. Sugawa
{"title":"A 200-μV/e- CMOS image sensor with 100-ke- full well capaclty","authors":"S. Adachi, Woonghee Lee, N. Akahane, H. Oshikubo, K. Mizobuchi, S. Sugawa","doi":"10.1109/VLSIC.2007.4342690","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342690","url":null,"abstract":"A high sensitivity CMOS image sensor without the dynamic range (DR) trade-off has been developed by implementing the small floating diffusion (FD) capacitance in the lateral overflow integration capacitor (CS) embedded pixel circuit. A 1/4-inch VGA chip fabricated through 0.18-μm 2P3M process achieves 200-μV/e- conversion gain with 100-ke- full well capacity, 2.2-e-rms noise floor and 93-dB DR. The S/N ratio degradation at the detection node switch from FD to FD+CS is not visible.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132932833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 6Snm CMOS 基于6Snm CMOS的11gb /s 2.4 mW半速率双抽头DFE接收机
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342747
A. Rylyakov
{"title":"An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 6Snm CMOS","authors":"A. Rylyakov","doi":"10.1109/VLSIC.2007.4342747","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342747","url":null,"abstract":"A 2-tap DFE receiver, implemented in a standard digital 65 nm bulk CMOS process, is aggressively optimized for low power and area. The 0.22 mW/Gbps power/speed ratio of the receiver and core area of 30 mum times 40 mum are achieved by using a half-rate architecture, a sampling front end, soft-decision direct feedback equalization and rail-to-rail CMOS clocking. At 11 Gb/s (2.6mA from 0.9V supply), the BER is less than 10-14 with a PRBS7 test sequence passing through a 30\" channel (15dB of loss at 5.5GHz).","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133254640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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