{"title":"具有DFR直流恢复功能的5.2Gbps超传输集成交流耦合接收器","authors":"E. Fang, G. Asada, R. Kumar, S. Hale, M. Leary","doi":"10.1109/VLSIC.2007.4342755","DOIUrl":null,"url":null,"abstract":"A HyperTransportTM receiver with integrated AC coupling achieves an extended DC input common mode voltage without resorting to AC encoding like 8B10B. The receiver supports all HyperTransportTM Revision 3 (HT3) data rate from 2.4 Gbps to 5.2 Gbps. A decision feedback restore (DFR) method is used to counter baseline wander. The design is implemented in a 65 nm SOI CMOS process.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 5.2Gbps hypertransportTM integrated AC coupled receiver with DFR DC restore\",\"authors\":\"E. Fang, G. Asada, R. Kumar, S. Hale, M. Leary\",\"doi\":\"10.1109/VLSIC.2007.4342755\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A HyperTransportTM receiver with integrated AC coupling achieves an extended DC input common mode voltage without resorting to AC encoding like 8B10B. The receiver supports all HyperTransportTM Revision 3 (HT3) data rate from 2.4 Gbps to 5.2 Gbps. A decision feedback restore (DFR) method is used to counter baseline wander. The design is implemented in a 65 nm SOI CMOS process.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342755\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342755","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
摘要
集成交流耦合的HyperTransportTM接收器可以实现扩展的直流输入共模电压,而无需诉诸像8B10B这样的交流编码。接收端支持2.4 ~ 5.2 Gbps的所有HT3 (HyperTransportTM Revision 3)数据速率。采用决策反馈恢复(DFR)方法对抗基线漂移。该设计采用65nm SOI CMOS工艺实现。
A 5.2Gbps hypertransportTM integrated AC coupled receiver with DFR DC restore
A HyperTransportTM receiver with integrated AC coupling achieves an extended DC input common mode voltage without resorting to AC encoding like 8B10B. The receiver supports all HyperTransportTM Revision 3 (HT3) data rate from 2.4 Gbps to 5.2 Gbps. A decision feedback restore (DFR) method is used to counter baseline wander. The design is implemented in a 65 nm SOI CMOS process.