A 200-μV/e- CMOS image sensor with 100-ke- full well capaclty

2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI:10.1109/VLSIC.2007.4342690

S. Adachi, Woonghee Lee, N. Akahane, H. Oshikubo, K. Mizobuchi, S. Sugawa

引用次数: 14

Abstract

A high sensitivity CMOS image sensor without the dynamic range (DR) trade-off has been developed by implementing the small floating diffusion (FD) capacitance in the lateral overflow integration capacitor (CS) embedded pixel circuit. A 1/4-inch VGA chip fabricated through 0.18-μm 2P3M process achieves 200-μV/e- conversion gain with 100-ke- full well capacity, 2.2-e-rms noise floor and 93-dB DR. The S/N ratio degradation at the detection node switch from FD to FD+CS is not visible.

查看原文本刊更多论文

一种200 μ v /e的CMOS图像传感器，具有100克满阱容量

通过在横向溢出集成电容(CS)嵌入式像素电路中实现小浮动扩散(FD)电容，开发了一种无动态范围(DR)折衷的高灵敏度CMOS图像传感器。采用0.18 μm 2P3M工艺制作的1/4英寸VGA芯片，转换增益为200 μ v /e，满井容量为100 μ v /e，本底噪声为2.2 e-rms, dr为93 db，检测节点从FD切换到FD+CS时信噪比下降不明显。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2007 IEEE Symposium on VLSI Circuits

自引率

0.00%

发文量