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2007 IEEE Symposium on VLSI Circuits最新文献

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A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications 用于片上网络应用的5.1GHz 0.34mm2路由器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342758
S. Vangal, A. Singh, J. Howard, S. Dighe, N. Borkar, A. Alvandpour
{"title":"A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications","authors":"S. Vangal, A. Singh, J. Howard, S. Dighe, N. Borkar, A. Alvandpour","doi":"10.1109/VLSIC.2007.4342758","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342758","url":null,"abstract":"A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm2 router layout. In a 65nm eight-metal CMOS process, the router contains 210K transistors and operates at 5.1GHz at 1.2 V, while dissipating 945 mW.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123983700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Notice of Violation of IEEE Publication PrinciplesZero-Second-IF SiGe BiCMOS Satellite Radio Tuner Using a Dual RF/IF AGC Loop 违反IEEE发布原则的通知使用双RF/IF AGC环路的零秒中频SiGe BiCMOS卫星无线电调谐器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342722
A. Maxim, M. Gheorge, C. Turinici
{"title":"Notice of Violation of IEEE Publication PrinciplesZero-Second-IF SiGe BiCMOS Satellite Radio Tuner Using a Dual RF/IF AGC Loop","authors":"A. Maxim, M. Gheorge, C. Turinici","doi":"10.1109/VLSIC.2007.4342722","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342722","url":null,"abstract":"A 0.2 mum SiGe BiCMOS tuner for digital satellite audio radio applications was realized using a second-zero-IF dual conversion architecture with autonomous RF AGC and channel decoder controlled IF AGC. A single PLL drives both RF and IF mixers, resulting in a smaller die area and lower power dissipation. Providing a baseband I/Q output further reduces receiver's power due to a lower ADC and digital core operating frequency. SDARS tuner performance includes: 5dB noise figure, 55dB image rejection, -96 dBm input sensitivity, 100 mA current from a 3.3 V supply and 12 mm2 die area.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124651274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator RF2:带有分布式谐振时钟发生器的1GHz FIR滤波器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342759
V. Sathe, J. C. Kao, M. Papaefthymiou
{"title":"RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator","authors":"V. Sathe, J. C. Kao, M. Papaefthymiou","doi":"10.1109/VLSIC.2007.4342759","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342759","url":null,"abstract":"In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13 mum CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency over CV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01 GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130148587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator 一个1.2 v 77 db 7.5 mhz连续/离散时间级联ΣΔ调制器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342733
S.D. Kulchycki, R. Trofin, K. Vleugels, B. Wooley
{"title":"A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator","authors":"S.D. Kulchycki, R. Trofin, K. Vleugels, B. Wooley","doi":"10.1109/VLSIC.2007.4342733","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342733","url":null,"abstract":"A hybrid ΣΔ modulator combines the anti-aliasing filtering and high sampling rate advantages of a continuous-time first stage with a low-power discrete-time second stage. A 0.18-μm CMOS experimental prototype samples signals at 240 MHz and achieves 77 dB of dynamic range and a peak SNDR of 67 dB for a signal bandwidth of 7.5 MHz, while dissipating 63.6 mW of analog power from a 1.2-V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130631627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An Injection-Locked 5.2 GHz SoC Transceiver with On-Chip Antenna for Self-Powered RFID and Medical Sensor Applications 用于自供电RFID和医疗传感器应用的带片上天线的注入锁定5.2 GHz SoC收发器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342777
P. Popplewell, V. Karam, A. Shamim, J. Rogers, C. Plett
{"title":"An Injection-Locked 5.2 GHz SoC Transceiver with On-Chip Antenna for Self-Powered RFID and Medical Sensor Applications","authors":"P. Popplewell, V. Karam, A. Shamim, J. Rogers, C. Plett","doi":"10.1109/VLSIC.2007.4342777","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342777","url":null,"abstract":"A completely integrated 5.2 GHz BFSK transceiver, including on-chip antenna, suitable for self-powered RFID and medical sensor applications is presented. Averaged transmit and receive power consumptions are less than 1 mW, enabling on-chip ultracapacitors to serve as the power source. The solution has a 1.75 m communication range at 5 kb/s, which can be increased at the expense of the bit-rate, power consumption in the receiver, or by using off-chip antennas.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129173799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 85mV 40nW Process-Tolerant Subthreshold 8×8 FIR Filter in 130nm Technology 一种85mV 40nW制程容忍亚阈值8×8 130纳米技术FIR滤波器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342695
Myeong-Eun Hwang, Arijit Raychowdhury, Keejong Kim, Kaushik Roy
{"title":"A 85mV 40nW Process-Tolerant Subthreshold 8×8 FIR Filter in 130nm Technology","authors":"Myeong-Eun Hwang, Arijit Raychowdhury, Keejong Kim, Kaushik Roy","doi":"10.1109/VLSIC.2007.4342695","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342695","url":null,"abstract":"Subthreshold operation is limited by low performance and high susceptibility to process variation. We propose variation tolerant ultra-dynamic voltage scaling (UDVS), and as an example we present an 8 times 8 process-tolerant FIR filter, working in both superthreshold and subthreshold regions featuring adaptive beta-ratio modulation and integrated level converters. Measurements show that the filter works at 85 mV consuming 40 nW, and the proposed method can salvage circuits which potentially failed to operate due to variations.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116092304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
A 152mW Mobille Multimedia SoC with Fully Programmable 3D Graphics and MPEG4/H.264/JPEG 152mW移动多媒体SoC，具有完全可编程3D图形和MPEG4/H.264/JPEG
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342726
Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, J. Jeong, Euljoo Jeong, S. Lee, H. Yoo
{"title":"A 152mW Mobille Multimedia SoC with Fully Programmable 3D Graphics and MPEG4/H.264/JPEG","authors":"Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, J. Jeong, Euljoo Jeong, S. Lee, H. Yoo","doi":"10.1109/VLSIC.2007.4342726","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342726","url":null,"abstract":"We present a 152 mW multimedia SoC with MPEG4 codec, H.264 decoder, JPEG codec and fully programmable 3D graphics for mobile applications. The unified shader in 3D graphics engine provides fully programmable 3D graphics with 35% area and 28% power reduction. Logarithmic lighting engine and the specialized lighting instruction give 9.1Mvertices/s vertex fill rate. The merged JPEG/MPEG4 codec and the unified shader reduce the silicon area further and the SoC consumes 6.4 mm times 6.4 mm in 0.13 mum CMOS logic process.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133249885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors 具有可配置异构9 cpu和2矩阵处理器的多核SoC设计
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342717
M. Nakajima, H. Kondo, N. Okumura, N. Masui, Y. Takata, T. Nasu, H. Takata, T. Higuchi, M. Sakugawa, H. Yoneda, H. Fujiwara, K. Ishida, K. Ishimi, S. Kaneko, T. Itoh, M. Sato, O. Yamamoto, K. Arimoto
{"title":"Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors","authors":"M. Nakajima, H. Kondo, N. Okumura, N. Masui, Y. Takata, T. Nasu, H. Takata, T. Higuchi, M. Sakugawa, H. Yoneda, H. Fujiwara, K. Ishida, K. Ishimi, S. Kaneko, T. Itoh, M. Sato, O. Yamamoto, K. Arimoto","doi":"10.1109/VLSIC.2007.4342717","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342717","url":null,"abstract":"A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The configurable heterogeneous architecture with 9 CPUs and 2 matrix processors reduced 45% power consumption. The performance-oriented multi-bank matrix processor with 2-read-1-write calculation and background I/O operation is adopted. The 1 GHz CPU is realized by the delay management network applied for any kinds of applications and process technologies.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114797460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 75GHz PLL Front-End Integration in 65nm SOI CMOS Technology 基于65nm SOI CMOS技术的75GHz锁相环前端集成
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342703
Daeik D. Kim, Jonghae Kim, J. Plouchart, Choongyeun Cho, D. Lim, Weipeng Li, R. Trzcinski
{"title":"A 75GHz PLL Front-End Integration in 65nm SOI CMOS Technology","authors":"Daeik D. Kim, Jonghae Kim, J. Plouchart, Choongyeun Cho, D. Lim, Weipeng Li, R. Trzcinski","doi":"10.1109/VLSIC.2007.4342703","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342703","url":null,"abstract":"A 75GHz PLL front-end, composed of complementary LC VCO, a buffer with AC coupling, and a static CML latch divider, is integrated in 65 nm SOI CMOS technology. The circuitry is developed with milli-meter wave link specifications, technology consideration, process variation, and topology selections. The PLL front-end achieves 5.9% tuning range centered at 73.4GHz and free-running phase noise of -1 lOdBc/Hz at 10MHz offset with 71mW.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"126 30","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113940119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2-GHz Direct Sampling Delta-Sigma Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL 带40ghz采样时钟和片上锁相环的2ghz直接采样Delta-Sigma可调谐接收器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342763
T. Chalvatzis, T. Dickson, S. Voinigescu
{"title":"A 2-GHz Direct Sampling Delta-Sigma Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL","authors":"T. Chalvatzis, T. Dickson, S. Voinigescu","doi":"10.1109/VLSIC.2007.4342763","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342763","url":null,"abstract":"This paper presents a 2-GHz tunable direct sampling DeltaSigma receiver with 40-GHz sampling clock and on-chip PLL, fabricated in a production 130-nm SiGe BiCMOS process. The measured SFDR and SNDR are 59 dB and 59.84 dB, respectively, over a bandwidth of 60 MHz, and the effective number of bits (ENOB) equals 9.65. Compared to the case where an external low-noise 40-GHz clock was used, no SNDR degradation was observed when the on-chip VCO and PLL were employed. The entire receiver with PLL occupies an area of 1.58 times 2.39 mm2 and consumes 2.19 W when powered from a 2.5-V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115782520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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