RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator

V. Sathe, J. C. Kao, M. Papaefthymiou
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引用次数: 14

Abstract

In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13 mum CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency over CV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01 GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.
RF2:带有分布式谐振时钟发生器的1GHz FIR滤波器
本文介绍了一种带有分布式谐振时钟发生器和片上电感器的1ghz两相谐振时钟FIR滤波器测试芯片RF2的设计和实验验证。RF2采用0.13 μ m CMOS工艺制造,谐振功耗为124mW,时钟功率仅占总功率的16%。RF2采用全ASIC设计流程实现,比CV2f实现84%的时钟功率效率,是所有完全集成的谐振时钟芯片中最高的。谐振频率为1.01 GHz, RF2报告了迄今为止谐振时钟数据通路的最高工作频率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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