{"title":"一个1.2 v 77 db 7.5 mhz连续/离散时间级联ΣΔ调制器","authors":"S.D. Kulchycki, R. Trofin, K. Vleugels, B. Wooley","doi":"10.1109/VLSIC.2007.4342733","DOIUrl":null,"url":null,"abstract":"A hybrid ΣΔ modulator combines the anti-aliasing filtering and high sampling rate advantages of a continuous-time first stage with a low-power discrete-time second stage. A 0.18-μm CMOS experimental prototype samples signals at 240 MHz and achieves 77 dB of dynamic range and a peak SNDR of 67 dB for a signal bandwidth of 7.5 MHz, while dissipating 63.6 mW of analog power from a 1.2-V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator\",\"authors\":\"S.D. Kulchycki, R. Trofin, K. Vleugels, B. Wooley\",\"doi\":\"10.1109/VLSIC.2007.4342733\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A hybrid ΣΔ modulator combines the anti-aliasing filtering and high sampling rate advantages of a continuous-time first stage with a low-power discrete-time second stage. A 0.18-μm CMOS experimental prototype samples signals at 240 MHz and achieves 77 dB of dynamic range and a peak SNDR of 67 dB for a signal bandwidth of 7.5 MHz, while dissipating 63.6 mW of analog power from a 1.2-V supply.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342733\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342733","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator
A hybrid ΣΔ modulator combines the anti-aliasing filtering and high sampling rate advantages of a continuous-time first stage with a low-power discrete-time second stage. A 0.18-μm CMOS experimental prototype samples signals at 240 MHz and achieves 77 dB of dynamic range and a peak SNDR of 67 dB for a signal bandwidth of 7.5 MHz, while dissipating 63.6 mW of analog power from a 1.2-V supply.
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