M. Nakajima, H. Kondo, N. Okumura, N. Masui, Y. Takata, T. Nasu, H. Takata, T. Higuchi, M. Sakugawa, H. Yoneda, H. Fujiwara, K. Ishida, K. Ishimi, S. Kaneko, T. Itoh, M. Sato, O. Yamamoto, K. Arimoto
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Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors
A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The configurable heterogeneous architecture with 9 CPUs and 2 matrix processors reduced 45% power consumption. The performance-oriented multi-bank matrix processor with 2-read-1-write calculation and background I/O operation is adopted. The 1 GHz CPU is realized by the delay management network applied for any kinds of applications and process technologies.
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