{"title":"RF2:带有分布式谐振时钟发生器的1GHz FIR滤波器","authors":"V. Sathe, J. C. Kao, M. Papaefthymiou","doi":"10.1109/VLSIC.2007.4342759","DOIUrl":null,"url":null,"abstract":"In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13 mum CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency over CV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01 GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"105 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator\",\"authors\":\"V. Sathe, J. C. Kao, M. Papaefthymiou\",\"doi\":\"10.1109/VLSIC.2007.4342759\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13 mum CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency over CV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01 GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"105 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342759\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342759","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
摘要
本文介绍了一种带有分布式谐振时钟发生器和片上电感器的1ghz两相谐振时钟FIR滤波器测试芯片RF2的设计和实验验证。RF2采用0.13 μ m CMOS工艺制造,谐振功耗为124mW,时钟功率仅占总功率的16%。RF2采用全ASIC设计流程实现,比CV2f实现84%的时钟功率效率,是所有完全集成的谐振时钟芯片中最高的。谐振频率为1.01 GHz, RF2报告了迄今为止谐振时钟数据通路的最高工作频率。
RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator
In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13 mum CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency over CV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01 GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.