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A Low Power Sigma-Delta Modulator Using Class-C Inverter 基于c类逆变器的低功耗Sigma-Delta调制器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342734
Youngcheol Chae, G. Han
{"title":"A Low Power Sigma-Delta Modulator Using Class-C Inverter","authors":"Youngcheol Chae, G. Han","doi":"10.1109/VLSIC.2007.4342734","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342734","url":null,"abstract":"In switched capacitor sigma-delta (SigmaDelta) analog-to-digital converters (ADCs), an operational transconductance amplifier (OTA) is the main building block and consumes most of power. This paper proposes that the OTAs can be replaced with class-C inverters for low-power consumption without sacrificing the performance. A second order SigmaDelta modulator using class-C inverter technique is fabricated with a 0.35-mum CMOS process, occupies 3024 mum2 , dissipates 5.6-muW under 1.2 V supply-voltage, and provides 63-dB/72-dB/76-dB SNDR/SNR/DR over 8-kHz signal bandwidth.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124000922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A 1.41W H.264/AVC Real-Time Encoder SOC for HDTV1080P HDTV1080P的1.41W H.264/AVC实时编码器SOC
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342716
Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, S. Ishiwata, M. Nakagawa, S. Goto, T. Ikenaga
{"title":"A 1.41W H.264/AVC Real-Time Encoder SOC for HDTV1080P","authors":"Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, S. Ishiwata, M. Nakagawa, S. Goto, T. Ikenaga","doi":"10.1109/VLSIC.2007.4342716","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342716","url":null,"abstract":"A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5 Gbps 64 Mb system-in-silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.18 m CMOS technology, the SoC core occupies 27.1 mm die area and consumes 1.41 W at 200MHz in typical work conditions.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"40 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126175255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
An 8.6mW 12.5Mvertices/s 800MOPS 8.91mm2 Stream Processor Core for Mobile Graphics and Video Applications 8.6mW 12.5Mvertices/s 800MOPS 8.91mm2流处理器核心，用于移动图形和视频应用
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342725
You-Ming Tsao, Chin-Hsiang Chang, Yu-Cheng Lin, Shao-Yi Chien, Liang-Gee Chen
{"title":"An 8.6mW 12.5Mvertices/s 800MOPS 8.91mm2 Stream Processor Core for Mobile Graphics and Video Applications","authors":"You-Ming Tsao, Chin-Hsiang Chang, Yu-Cheng Lin, Shao-Yi Chien, Liang-Gee Chen","doi":"10.1109/VLSIC.2007.4342725","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342725","url":null,"abstract":"An 8.6 mW stream processor core for mobile applications is implemented with 8.91 mm2 area in 0.18 mum CMOS technology at 50 MHz. The adaptive multi-thread architecture with configurable memory array and geometry-content-aware technique are proposed to reduce power consumption while achieving 12.5 Mvertices/s for 3D graphics and motion estimation with search range {H[-24,24),V[-16,16]} for CIF (352times288) 30 fps video encoding.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126381343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 6.5GHz 54mW 64-bit Parity-Checking Adder for 65nm Fault-Tolerant Microprocessor Execution Cores 用于65nm容错微处理器执行核的6.5GHz 54mW 64位奇偶校验加法器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342760
S. Mathew, M. Anders, R. Krishnamurthy, S. Borkar
{"title":"A 6.5GHz 54mW 64-bit Parity-Checking Adder for 65nm Fault-Tolerant Microprocessor Execution Cores","authors":"S. Mathew, M. Anders, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2007.4342760","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342760","url":null,"abstract":"This paper describes a parity-checking fault-tolerant adder designed for 6.5 GHz operation with total power consumption of 54 mW, targeted for 65 nm 64-bit microprocessor execution cores. The adder is fully self-checking and guarantees 100% coverage of single-faults (including multi-bit output errors originating from single-faults) on any sequential/combinational node in the design. The sparse-tree design enables partial pre-computation of the critical carry-parities, resulting in 33% reduction in parity-computation delay overhead with a low 6% area overhead for fault-detection.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129908897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An Integrated 1.2V-to-6V CMOS Charge-Pump for Electret Earphone 用于驻极体耳机的集成1.2 v - 6v CMOS电荷泵
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342678
Chun-Yen Tseng, Shih-Chieh Chen, T. Shia, Po-Chiun Huang
{"title":"An Integrated 1.2V-to-6V CMOS Charge-Pump for Electret Earphone","authors":"Chun-Yen Tseng, Shih-Chieh Chen, T. Shia, Po-Chiun Huang","doi":"10.1109/VLSIC.2007.4342678","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342678","url":null,"abstract":"This work proposes a new charge pump design that achieves a high set-up ratio for electret earphone driving circuits. The voltage pumping cell is based on Cockcroft-Walton topology to achieve small area with constant MOS capacitor value under low system voltage operation. A 6-V output voltage is regulated by a PFM-based loop. This loop includes a new switched-capacitor divider as a part of the sensing circuitry. All the components are integrated in a standard 0.18 mum CMOS. Measurement results show that with 1.2 V supply, the output voltage is around 6 V with 30 mV output ripple. The maximum output driving current is up to 0.7 mA.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126788314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 2.2 Gb/s DQPSK Baseband Receiver in 90-nm CMOS for 60 GHz Wireless Links 用于60 GHz无线链路的90纳米CMOS 2.2 Gb/s DQPSK基带接收器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342764
Minghui Chen, M. Chang
{"title":"A 2.2 Gb/s DQPSK Baseband Receiver in 90-nm CMOS for 60 GHz Wireless Links","authors":"Minghui Chen, M. Chang","doi":"10.1109/VLSIC.2007.4342764","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342764","url":null,"abstract":"This paper presents a CMOS DQPSK direct-conversion baseband receiver that can deliver 2.2 Gb/s data rate to support 1920times1080 interlaced HDTV wireless transmission in the unlicensed 60 GHz band. The receiver system architecture and major circuit blocks are described. Implemented in the 90 nm CMOS process, the receiver achieves a maximum data rate of 2.4 Gb/s with measured BER of 10-9. It is operated under IV DC supply voltage with 85 mW of total power consumption.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127124623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Skew-Tolerant Global Synchronization Based on Periodically All-in-Phase Clocking for Multi-Core SOC Platforms 基于周期性全相时钟的多核SOC平台容斜全局同步
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342697
A. Shibayama, K. Nose, S. Torii, M. Mizuno, M. Edahiro
{"title":"Skew-Tolerant Global Synchronization Based on Periodically All-in-Phase Clocking for Multi-Core SOC Platforms","authors":"A. Shibayama, K. Nose, S. Torii, M. Mizuno, M. Edahiro","doi":"10.1109/VLSIC.2007.4342697","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342697","url":null,"abstract":"A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, and loosely balanced global clock distribution serves to ease chip-timing design while maintaining deterministic chip behavior.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130368536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter 一个12gs /s相位校准CMOS数模转换器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342769
J. Savoj, A. Abbasfar, A. Amirkhany, M. Jeeradit, B. Garlepp
{"title":"A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter","authors":"J. Savoj, A. Abbasfar, A. Amirkhany, M. Jeeradit, B. Garlepp","doi":"10.1109/VLSIC.2007.4342769","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342769","url":null,"abstract":"A 12-GS/s 8-bit Digital-to-Analog Converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350mum and achieves INL and DNL of 0.31 and 0.28 LSB. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"602 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Class AB Amplifier for LCD Driver 用于LCD驱动的AB类放大器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342693
R. Ito, T. Itakura, H. Minamizaki
{"title":"A Class AB Amplifier for LCD Driver","authors":"R. Ito, T. Itakura, H. Minamizaki","doi":"10.1109/VLSIC.2007.4342693","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342693","url":null,"abstract":"For the LCDs used in the mobile terminals, low power dissipation and high speed operation are required. In this paper, high speed, low power dissipation and rail-to-rail input/output class AB amplifier is proposed. In the proposed circuit, the number of current paths was reduced and the phase compensation suitable for high speed operation was employed. The proposed circuit was fabricated using 0.13 mum process. The supply voltage is 5 V and the current dissipation is 2 muA. The settling time within 2 musec at both rising and falling edges was achieved.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128328116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A PVT Tolerant PLL with On-Chip Loop-Transfer-Function Calibration Circuit 带片上环传递功能校准电路的PVT容限锁相环
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342731
M. Kondou, T. Mori
{"title":"A PVT Tolerant PLL with On-Chip Loop-Transfer-Function Calibration Circuit","authors":"M. Kondou, T. Mori","doi":"10.1109/VLSIC.2007.4342731","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342731","url":null,"abstract":"A PVT tolerant PLL architecture which uses two on-chip digital calibration circuits to maintain loop transfer function is presented. Test chips with 9 conditions, MOSes, resistors and capacitors, were fabricated in a 90 nm CMOS technology. Experimental results show that the phase noise remains + 2dBc/Hz within 10 MHz offset under any PVT condition.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131876907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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