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2007 IEEE Symposium on VLSI Circuits最新文献

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Effect of Power Supply Noise on SRAM Dynamic Stability 电源噪声对SRAM动态稳定性的影响
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342772
M. Khellah, D. Khalil, D. Somasekhar, Yehea Ismail, T. Karnik, Vivek De
{"title":"Effect of Power Supply Noise on SRAM Dynamic Stability","authors":"M. Khellah, D. Khalil, D. Somasekhar, Yehea Ismail, T. Karnik, Vivek De","doi":"10.1109/VLSIC.2007.4342772","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342772","url":null,"abstract":"We present both simulation results and test-chip measurements on the effect of power supply noise on SRAM dynamic cell stability. Results indicate that to accurately capture the effect of supply droop on bit failure rate, not only the DC amplitude of the noise needs to be considered as commonly practiced, but also its phase and frequency.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134099263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A High Efficiency DC-DC Converter Using 2nH On-Chip Inductors 采用2nH片上电感的高效率DC-DC变换器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342750
J. Wibben, R. Harjani
{"title":"A High Efficiency DC-DC Converter Using 2nH On-Chip Inductors","authors":"J. Wibben, R. Harjani","doi":"10.1109/VLSIC.2007.4342750","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342750","url":null,"abstract":"Historically buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve high efficiency. In this paper we exploit on-chip magnetic coupling in the proposed stacked interleaved topology to enable high efficiency buck converters to be realized with 2 nH moderate-Q on-chip inductors. The measured conversion efficiency for a prototype circuit implemented in a 130-nm CMOS technology was over double that of a linear converter for low output voltages rising to a peak value of 77.9% for a 0.9 V output.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134321017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A Wide Locking Range and Low Power V-band Frequency Divider in 90nm CMOS 90nm CMOS宽锁定范围低功耗v带分频器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342745
Q. Gu, Zhiwei Xu, M. Chang
{"title":"A Wide Locking Range and Low Power V-band Frequency Divider in 90nm CMOS","authors":"Q. Gu, Zhiwei Xu, M. Chang","doi":"10.1109/VLSIC.2007.4342745","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342745","url":null,"abstract":"A new topology for injection locked frequency divider (ILFD) is proposed to achieve high speed, wide locking range and quadrature phase operation. The dividing mechanism is analyzed and agrees well with the simulation. A prototype is implemented in TSMC 90 nm CMOS and realizes 4 GHz locking range (55.8 GHz-59.8 GHz) with -3 dBm input power and 5 mW DC power consumption. The divider attains the widest locking range with the lowest power consumption to date for V-band frequency dividing applications.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"53 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133106461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Precursor ISI Reduction in High-Speed I/O 高速I/O前驱体ISI减少
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342687
Jihong Ren, Haechang Lee, Qi Lin, Brian S. Leibowitz, Ehung Chen, Dan Oh, F. Lambrecht, Vladimir Stojanovic, C. Yang, Jared Zerbe
{"title":"Precursor ISI Reduction in High-Speed I/O","authors":"Jihong Ren, Haechang Lee, Qi Lin, Brian S. Leibowitz, Ehung Chen, Dan Oh, F. Lambrecht, Vladimir Stojanovic, C. Yang, Jared Zerbe","doi":"10.1109/VLSIC.2007.4342687","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342687","url":null,"abstract":"To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the interaction between equalization adaptation and clock-data recovery (CDR), coupled with transmitter peak-power constraint. To minimize the impact of precursor ISI on the bit-error-rate (BER), we propose a new method of adapting CDR phase for maximum voltage margin.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127668093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A 0.5-V 1.9-GHz low-power phase-locked loop in 0.18-μm CMOS 0.5 v 1.9 ghz低功耗锁相环，0.18 μm CMOS
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342699
H. Hsieh, Chung-Ting Lu, Liang-Hung Lu
{"title":"A 0.5-V 1.9-GHz low-power phase-locked loop in 0.18-μm CMOS","authors":"H. Hsieh, Chung-Ting Lu, Liang-Hung Lu","doi":"10.1109/VLSIC.2007.4342699","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342699","url":null,"abstract":"Implemented in a standard 0.18-mum CMOS process, a 0.5-V 1.9-GHz low-power phase-locked loop (PLL) is presented. Due to the use of the forward-body-bias technique, the threshold voltage of the MOSFETs is effectively reduced, making it possible to operate the PLL at an ultra-low supply voltage. In addition, various techniques for low-power and low-voltage operations are also adopted in the design of the building blocks. With a dc power consumption of 4.5 mW, the fabricated PLL measures in-band and out-of-band phase noise of -83.4 dBc/Hz and -135.3 dBc/Hz at 100-kHz and 10-MHz frequency offset, respectively.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115411597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation 利用置乱时间-数字转换器和数字相关的低抖动1.6 GHz乘法DLL
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342700
Belal M. Helal, Matthew Z. StraayerP, Michael H. PerrottP
{"title":"A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation","authors":"Belal M. Helal, Matthew Z. StraayerP, Michael H. PerrottP","doi":"10.1109/VLSIC.2007.4342700","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342700","url":null,"abstract":"This paper presents a 1.6 GHz multiplying delay-locked loop (MDLL) that leverages time-to-digital conversion and a digital correlation technique to achieve low deterministic jitter while still maintaining low random jitter. A proposed time-to-digital converter consists of a ring oscillator that is gated on and off to accurately measure time and scramble the measurement's residual error. Using a 50 MHz reference, the prototype system has measured reference spurs less than -59 dBc and an overall measured jitter of 1.41 ps.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114589918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
A Fully Integrated Low-IF Image Reject Receiver for T-DMB and DAB Applications 一个完全集成的低中频图像抑制接收器，用于T-DMB和DAB应用
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342721
Kyoohyun Lim, Sunki Min, Myung-woon Hwang, Sang-Hoon Lee, Tae-Jin Kim, Sungho Beck, Sungmin Ock, Jeong-Cheol Lee, H. Jung, Seokyong Hong, Jongsik Kim, Sangwoo Han
{"title":"A Fully Integrated Low-IF Image Reject Receiver for T-DMB and DAB Applications","authors":"Kyoohyun Lim, Sunki Min, Myung-woon Hwang, Sang-Hoon Lee, Tae-Jin Kim, Sungho Beck, Sungmin Ock, Jeong-Cheol Lee, H. Jung, Seokyong Hong, Jongsik Kim, Sangwoo Han","doi":"10.1109/VLSIC.2007.4342721","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342721","url":null,"abstract":"This paper describes a fully integrated low-IF image reject receiver for triple-band T-DMB and DAB applications. The receiver features an efficient local oscillator (LO) frequency planning using a wideband low phase noise voltage-controlled oscillator (VCO) for improved low-IF receiver performance. The tuning range of the VCO is measured from 2.65 to 3.95GHz covering all the required frequency bands (Band-II, Band-Ill, and L-Band). The receiver shows a measured noise figure (NF) of under 2dB, thereby achieving a sensitivity of lower than -100dBm with 100mW power consumption. The maximum input signal level of the receiver is lOdBm, resulting in HOdB dynamic range. Total image rejection of over 50dB is achieved. The receiver is fabricated in a 0.25-mum BiCMOS process and packaged in a 5mm x 5mm 32-pin MLF package.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116185795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications 用于移动应用的2.8至67.2mW低功耗和功耗感知H.264编码器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342727
Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Shao-Yi Chien, Liang-Gee Chen
{"title":"2.8 to 67.2mW Low-Power and Power-Aware H.264 Encoder for Mobile Applications","authors":"Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Shao-Yi Chien, Liang-Gee Chen","doi":"10.1109/VLSIC.2007.4342727","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342727","url":null,"abstract":"A 2.8 to 67.2 mW H.264 encoder is implemented on a 12.8 mm2 die with 0.18 mum CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
An Ultra Fast Fixed Frequency Buck Converter with Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications 具有最大充电电流控制和自适应延迟补偿的超快速固定频率降压转换器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342753
Feng Su, W. Ki, C. Tsui
{"title":"An Ultra Fast Fixed Frequency Buck Converter with Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications","authors":"Feng Su, W. Ki, C. Tsui","doi":"10.1109/VLSIC.2007.4342753","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342753","url":null,"abstract":"A buck converter with maximum charging current control in achieving high tracking speed is presented. An adaptive delay compensation scheme is employed to keep the switching frequency at 850 kHz within plusmn2.5% across the whole operation range. The integrated buck converter was fabricated using a 0.35 mum CMOS process and all functions are verified by extensive measurements.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132681672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 60-GHz CMOS Receiver with Frequency Synthesizer 带频率合成器的60ghz CMOS接收机
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342702
T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana, H. Hoshino, Y. Yoshihara, Y. Tsutsumi, I. Seto
{"title":"A 60-GHz CMOS Receiver with Frequency Synthesizer","authors":"T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana, H. Hoshino, Y. Yoshihara, Y. Tsutsumi, I. Seto","doi":"10.1109/VLSIC.2007.4342702","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342702","url":null,"abstract":"A 60-GHz receiver (RX) chip fabricated in 90 nm CMOS process is reported. The RX chip consists of an LNA, a downconversion mixer and a phase-locked loop synthesizer. The RX chip is capable of generating LO signal from phase-locked synthesizer. Measured power gain and NF of 22 dB and 8.4 dB were obtained at 61.5 GHz. These results indicate the possibility of realization of CMOS single-chip 60-GHz transceiver.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132913605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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