{"title":"采用2nH片上电感的高效率DC-DC变换器","authors":"J. Wibben, R. Harjani","doi":"10.1109/VLSIC.2007.4342750","DOIUrl":null,"url":null,"abstract":"Historically buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve high efficiency. In this paper we exploit on-chip magnetic coupling in the proposed stacked interleaved topology to enable high efficiency buck converters to be realized with 2 nH moderate-Q on-chip inductors. The measured conversion efficiency for a prototype circuit implemented in a 130-nm CMOS technology was over double that of a linear converter for low output voltages rising to a peak value of 77.9% for a 0.9 V output.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"37","resultStr":"{\"title\":\"A High Efficiency DC-DC Converter Using 2nH On-Chip Inductors\",\"authors\":\"J. Wibben, R. Harjani\",\"doi\":\"10.1109/VLSIC.2007.4342750\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Historically buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve high efficiency. In this paper we exploit on-chip magnetic coupling in the proposed stacked interleaved topology to enable high efficiency buck converters to be realized with 2 nH moderate-Q on-chip inductors. The measured conversion efficiency for a prototype circuit implemented in a 130-nm CMOS technology was over double that of a linear converter for low output voltages rising to a peak value of 77.9% for a 0.9 V output.\",\"PeriodicalId\":261092,\"journal\":{\"name\":\"2007 IEEE Symposium on VLSI Circuits\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"37\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2007.4342750\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2007.4342750","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A High Efficiency DC-DC Converter Using 2nH On-Chip Inductors
Historically buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve high efficiency. In this paper we exploit on-chip magnetic coupling in the proposed stacked interleaved topology to enable high efficiency buck converters to be realized with 2 nH moderate-Q on-chip inductors. The measured conversion efficiency for a prototype circuit implemented in a 130-nm CMOS technology was over double that of a linear converter for low output voltages rising to a peak value of 77.9% for a 0.9 V output.