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2007 IEEE Symposium on VLSI Circuits最新文献

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A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique 采用预充电技术的14b低功耗流水线A/D转换器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342712
K. Honda, Zheng Liu, M. Furuta, S. Kawahito
{"title":"A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique","authors":"K. Honda, Zheng Liu, M. Furuta, S. Kawahito","doi":"10.1109/VLSIC.2007.4342712","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342712","url":null,"abstract":"A pre-charging technique to improve the settling response of pipeline stages is demonstrated in a Mbit pipeline A/D converter (ADC). The prototype ADC fabricated in a 0.25 mum CMOS process consumes 102 mW at 30 MSample/s. Measured SNDR and SFDR are 70.7 dB and 82.8 dB, respectively.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133825178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations 一种65纳米移动多媒体应用处理器，具有自适应电源管理方案，以补偿变化
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342728
H. Mair, A. Wang, G. Gammie, D. Scott, P. Royannez, S. Gururajarao, M. Chau, R. Lagerquist, L. Ho, M. Basude, N. Culp, A. Sadate, D. Wilson, F. Dahan, J. Song, B. Carlson, U. Ko
{"title":"A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations","authors":"H. Mair, A. Wang, G. Gammie, D. Scott, P. Royannez, S. Gururajarao, M. Chau, R. Lagerquist, L. Ho, M. Basude, N. Culp, A. Sadate, D. Wilson, F. Dahan, J. Song, B. Carlson, U. Ko","doi":"10.1109/VLSIC.2007.4342728","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342728","url":null,"abstract":"In this paper we present the SmartReflextrade power management techniques implemented on the OMAP3430 Mobile Multimedia Applications Processor. By using multiple voltage domains, fine grain power domains, split-rail memories, and adaptive compensation, SoC active power reduction of 66% and leakage power reduction of 2~3 orders of magnitude was achieved. OMAP3430 contains more than 150M transistors.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133697437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise 一种用于纳秒级电源噪声的片上高压电源消声器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342683
Y. Nakamura, M. Takamiya, T. Sakurai
{"title":"An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise","authors":"Y. Nakamura, M. Takamiya, T. Sakurai","doi":"10.1109/VLSIC.2007.4342683","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342683","url":null,"abstract":"An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The canceller fabricated with 90-nm CMOS achieves 68% noise reduction with 2.0% power increase. Under the same noise reduction conditions, the area penalty for the canceller is 1/77 and 1/45 of those for the additional on-chip decoupling capacitors and the power supply lines respectively.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133886972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 100μ a digital controller with transient enhancement for dynamic voltage output switching-type DC-DC converter 一种用于动态电压输出开关型DC-DC变换器的100μ A瞬态增强数字控制器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342751
Chun-Yen Tseng, Po-Chiun Huang
{"title":"A 100μ a digital controller with transient enhancement for dynamic voltage output switching-type DC-DC converter","authors":"Chun-Yen Tseng, Po-Chiun Huang","doi":"10.1109/VLSIC.2007.4342751","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342751","url":null,"abstract":"This paper presents a high efficiency digital controller for a switching type DC-DC converter with excellent static and dynamic performance. This digital PWM controller integrates a PID-like control mechanism and a new predictive interpolation technique to guarantee large signal stability and fast dynamic response. To support the proposed control scheme, an ADC structure that can sequentially sample the output level is proposed. All the circuit architectures are for low power thus achieve the maximum 96% power efficiency with 0.35 W output.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133262361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS 90nm CMOS的7b 1.1GS/s可重构时间交错ADC
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342768
Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Z. Soe, T. Aytur, R. Yan
{"title":"A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS","authors":"Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Z. Soe, T. Aytur, R. Yan","doi":"10.1109/VLSIC.2007.4342768","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342768","url":null,"abstract":"A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, Fs, to accommodate different operation scenarios. The main offset and gain mismatches between four sub-ADCs are modulated to the frequency of F/2 by the reference-and opamp-sharing techniques. Fabricated in 90 nm CMOS, the 7 bit ADC has an ENOB of 6.5 at 1.1 GHz sampling rate. The I/Q ADCs totally consume power of 92 mW from a 1.3 V supply.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122146246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
76GHz CMOS Voltage-Controlled Oscillator with 7% Frequency Tuning Range 具有7%频率调谐范围的76GHz CMOS压控振荡器
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342704
K. Ishibashi, M. Motoyoshi, N. Kobayashi, M. Fujishima
{"title":"76GHz CMOS Voltage-Controlled Oscillator with 7% Frequency Tuning Range","authors":"K. Ishibashi, M. Motoyoshi, N. Kobayashi, M. Fujishima","doi":"10.1109/VLSIC.2007.4342704","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342704","url":null,"abstract":"To improve the tuning range and phase noise in W-band CMOS voltage-controlled oscillators (VCOs), we propose a new ring-shaped transmission line for the LC tank. As a result, a VCO with a 76.5 GHz center frequency, a tuning range of 7% and a phase noise of -110.6 dBc/Hz was realized by using a 90 nm CMOS 1P6M process.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125882379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A CMOS UWB-IR Receiver Analog Front End with Intermittent Operation 一种间歇操作的CMOS UWB-IR接收机模拟前端
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342776
T. Terada, R. Fujiwara, G. Ono, T. Norimatsu, T. Nakagawa, K. Mizugaki, M. Miyazaki, K. Suzuki, K. Yano, A. Maeki, Y. Ogata, S. Kobayashi, N. Koshizuka, K. Sakamura
{"title":"A CMOS UWB-IR Receiver Analog Front End with Intermittent Operation","authors":"T. Terada, R. Fujiwara, G. Ono, T. Norimatsu, T. Nakagawa, K. Mizugaki, M. Miyazaki, K. Suzuki, K. Yano, A. Maeki, Y. Ogata, S. Kobayashi, N. Koshizuka, K. Sakamura","doi":"10.1109/VLSIC.2007.4342776","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342776","url":null,"abstract":"A low power receiver analog front end (AFE) for ultra-wideband impulse radio (UWB-IR) was developed in 0.18 mum CMOS. All circuits of the receiver AFE operate intermittently with a sampling clock of an analog-digital converter (ADC). The sampling rate of the ADC is equal to pulse repetition frequency of the received signals. Power consumption of the receiver AFE is decreased 60% by intermittent operation without degrading of receiver sensitivity. As a result, the power consumption of the receiver AFE is 38 mW at 258 kbps data rate.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"859 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123974190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 5 kV HBM transformer-based ESD protected 5-6 GHz LNA 基于5 kV HBM变压器的ESD保护5-6 GHz LNA
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342677
J. Borremans, S. Thijs, P. Wambacq, D. Linten, Yves Rolain, Maarten Kuijk
{"title":"A 5 kV HBM transformer-based ESD protected 5-6 GHz LNA","authors":"J. Borremans, S. Thijs, P. Wambacq, D. Linten, Yves Rolain, Maarten Kuijk","doi":"10.1109/VLSIC.2007.4342677","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342677","url":null,"abstract":"Integrated designs in deep-submicron CMOS require ESD protection for their I/O pins. Since CMOS scaling drastically lowers the breakdown voltage of a MOS transistor, the available design window for ESD protection is narrowing. An inductor-based ESD protection offers superb protection but is severely area consuming. In this paper we propose a transformer-based ESD protection for inductor-based LNAs. We demonstrate that the proposed technique offers excellent ESD protection and RF performance without the loss of area.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123335068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM 6.6+ GHz低Vmin，读取和半选择无干扰的1.2 Mb SRAM
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342738
R. Joshi, R. Houle, K. Batson, D. Rodko, P. Patel, W. Huott, R. Franch, Y. Chan, D. Plass, S. Wilson, P. Wang
{"title":"6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM","authors":"R. Joshi, R. Houle, K. Batson, D. Rodko, P. Patel, W. Huott, R. Franch, Y. Chan, D. Plass, S. Wilson, P. Wang","doi":"10.1109/VLSIC.2007.4342738","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342738","url":null,"abstract":"A fully functional read and half select disturb-free 1.2 Mb SRAM is demonstrated. Measured results show an operating range of 0.4 V to 1.5 V and -25degC to 100degC, speed of 6.6+ GHz at IV, 25degC and yield of 90-100%.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115187938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers 带有1.2 mw双向收发器的8gbps低延迟多滴片上传输线互连
2007 IEEE Symposium on VLSI Circuits Pub Date : 2007-06-14 DOI: 10.1109/VLSIC.2007.4342688
H. Ito, M. Kimura, K. Okada, K. Masu
{"title":"A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers","authors":"H. Ito, M. Kimura, K. Okada, K. Masu","doi":"10.1109/VLSIC.2007.4342688","DOIUrl":"https://doi.org/10.1109/VLSIC.2007.4342688","url":null,"abstract":"This paper proposes a multi-drop on-chip transmission line interconnect for high-speed on-chip buses. The proposed two-way transceiver serves as both Tx and Rx for on-chip transmission lines and can branch signals without delay degradation. The proposed interconnect, which has six two-way transceivers and 5-mm-long transmission line, performs 8 Gbps signaling with power dissipation of 7.1 mW.","PeriodicalId":261092,"journal":{"name":"2007 IEEE Symposium on VLSI Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124775687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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